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John,

Here's my understanding of the I and Q representation. You have to
sample at 90 degrees apart in order to resolve the properties
(modulation) of the Carrier frequency. Therefore you always have to
sample at four times the desired carrier. Think of it as an X and Y
coordinate system. If the X and Y axis are not 90 degrees apart, you
have a difficult time resolving the resultant vector.

There is a difference between "sample at four times the desired
carrier" 4X the frequency and "sample four times during the desired carrier cycle" (90,180,270, and 360) which can be done with a 2X frequency and the Tayloe detector. That first divide by two is still
a "50% duty cycle forcer" which is a requirement for the Tayloe detector to work.

73 Kees K5BCQ

Kees,

It would seem to me that two JK flip flops followed by 4 exclusive OR gates to get the 0 and 180 degree shifts, would be a great way to minimize the component costs and still be able to divide by 2 and get the four outputs you need for a four switched capacitor Tayloe detector. And you wouldn't lose any gain, which is kind of important in a receiver like this for lowest noise performance. And it would only take 2 chips total.

The exclusive OR gates would maintain the same delay with the 0 and 180 degree shifts as well as the 90 and 270 degree shifts. Just tie the unused input of each gate to either gnd or +5 to shift either 0 or 180 degrees.

The JK flip flop schematic I posted earlier seems to be the most symmetric way of getting the 0 and 90 degree shift to start with.

But I also notice that no one makes JK flip flops anymore, at least for the high speed CMOS stuff. I don't know why...

Maybe someone else knows?

Bill

windy10605@... wrote:

At 10:34 PM 10/27/2005, you wrote:

Kees,

It would seem to me that two JK flip flops followed by 4 exclusive OR
gates to get the 0 and 180 degree shifts, would be a great way to
minimize the component costs and still be able to divide by 2 and get
the four outputs you need for a four switched capacitor Tayloe
detector. And you wouldn't lose any gain, which is kind of important in
a receiver like this for lowest noise performance. And it would only
take 2 chips total.

The exclusive OR gates would maintain the same delay with the 0 and 180
degree shifts as well as the 90 and 270 degree shifts. Just tie the
unused input of each gate to either gnd or +5 to shift either 0 or 180
degrees.

The JK flip flop schematic I posted earlier seems to be the most
symmetric way of getting the 0 and 90 degree shift to start with.

But I also notice that no one makes JK flip flops anymore, at least for
the high speed CMOS stuff. I don't know why...

Hi Bill,


Maybe my memory has failed, but I think I had little difficulty finding a JK, think it was a 74AC109. I'm not sure why they would fall out of popularity unless there is something that is inherently slower due to the design. I think ANND gates are always faster than AND gates, which is why we see more types of NAND gates for example.

I missed your posting of the schematic, if you still have it, can you email it please.

Thanks,

Art

Maybe someone else knows?

Bill

windy10605@... wrote:

Kees,

Here is the file again. I did not post it to the files section. I was referring to the 74HC and 74AHC, high speed and advanced high speed CMOS.

Bill

KY1K wrote:

Here is the file again. I did not post it to the files section. I was referring to the 74HC and 74AHC, high speed and advanced high speed CMOS.

I'm probably working through the truth tables incorrectly, but I don't think this is a quadrature divide-by-2. It appears to be a quadrature divide-by-four.

Call the upper FF #1 and the lower FF #2, use the indicated 74xx73 which has a negative-edge-triggered clock, and have both reset as the initial condition, then:

JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (falling edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (falling edge)
10 01 0 0 -- after fourth clock (falling edge)

We are now back to the initial condition and the cycle repeats ad infinitum.

To get a quadrature divide by two, you need to toggle one flip-flop on the positive edge of the clock, and the other on the negative edge of the clock, as there are only a total of 4 edges in a 2x clock. This also implies the clock must be perfectly symmetrical, e.g. a 50% duty cycle.

If this is the case, you can use a D (with input tied to its own /Q), a J-K (with J and K both pulled high) or a T flip-flop, and run the clock through an exclusive-OR to each of the two flip-flop clock inputs. One Ex-Or will have its second input pulled high, the other pulled low, so you have a clock and its inverse with essentially equal delay. Thus, the flip-flop chosen can be either positive or negative edge triggered and you'll get the correct result.

The example circuit but with the inverted clock fed to FF #1 results in:

JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (rising edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (rising edge)
10 01 0 0 -- after fourth clock (falling edge)

And we have a quadrature divide-by-two.

Enjoy!

Lyle KK7P

That is the problem with /2 quadrature generation, you need a symmetrical input clock so you can use both edges to the clock. That is, if you are going to 25% clock phases for maximum gain. You can use a clock at less that the frequency of interest (sub-sampling) but your gain goes down.

If you have a symmetrical 2X clock you might as well use a doubler (analog or digital) and divide by 4 to get a 25% clock phase.


At 10:22 AM 10/28/2005, you wrote:

Here is the file again. I did not post it to the files section. I was
referring to the 74HC and 74AHC, high speed and advanced high speed CMOS.

I'm probably working through the truth tables incorrectly, but I don't
think this is a quadrature divide-by-2. It appears to be a quadrature
divide-by-four.

Call the upper FF #1 and the lower FF #2, use the indicated 74xx73 which
has a negative-edge-triggered clock, and have both reset as the initial
condition, then:

JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (falling edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (falling edge)
10 01 0 0 -- after fourth clock (falling edge)

We are now back to the initial condition and the cycle repeats ad infinitum.

To get a quadrature divide by two, you need to toggle one flip-flop on
the positive edge of the clock, and the other on the negative edge of
the clock, as there are only a total of 4 edges in a 2x clock. This
also implies the clock must be perfectly symmetrical, e.g. a 50% duty cycle.

If this is the case, you can use a D (with input tied to its own /Q), a
J-K (with J and K both pulled high) or a T flip-flop, and run the clock
through an exclusive-OR to each of the two flip-flop clock inputs. One
Ex-Or will have its second input pulled high, the other pulled low, so
you have a clock and its inverse with essentially equal delay. Thus,
the flip-flop chosen can be either positive or negative edge triggered
and you'll get the correct result.

The example circuit but with the inverted clock fed to FF #1 results in:

JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (rising edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (rising edge)
10 01 0 0 -- after fourth clock (falling edge)

And we have a quadrature divide-by-two.

Enjoy!

Lyle KK7P





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Cecil Bayona
KD5NWA
www.qrpradio.com

I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ...

KD5NWA wrote:

That is the problem with /2 quadrature generation, you need a
symmetrical input clock so you can use both edges to the clock. That
is, if you are going to 25% clock phases for maximum gain. You can
use a clock at less that the frequency of interest (sub-sampling) but
your gain goes down.

If you have a symmetrical 2X clock you might as well use a doubler
(analog or digital) and divide by 4 to get a 25% clock phase.


At 10:22 AM 10/28/2005, you wrote:

Here is the file again. I did not post it to the files section.

I was

referring to the 74HC and 74AHC, high speed and advanced high

speed CMOS.

I'm probably working through the truth tables incorrectly, but I don't
think this is a quadrature divide-by-2. It appears to be a quadrature
divide-by-four.

Call the upper FF #1 and the lower FF #2, use the indicated 74xx73 which
has a negative-edge-triggered clock, and have both reset as the initial
condition, then:

JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (falling edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (falling edge)
10 01 0 0 -- after fourth clock (falling edge)

We are now back to the initial condition and the cycle repeats ad

infinitum.

To get a quadrature divide by two, you need to toggle one flip-flop on
the positive edge of the clock, and the other on the negative edge of
the clock, as there are only a total of 4 edges in a 2x clock. This
also implies the clock must be perfectly symmetrical, e.g. a 50% duty

cycle.

If this is the case, you can use a D (with input tied to its own /Q), a
J-K (with J and K both pulled high) or a T flip-flop, and run the clock
through an exclusive-OR to each of the two flip-flop clock inputs. One
Ex-Or will have its second input pulled high, the other pulled low, so
you have a clock and its inverse with essentially equal delay. Thus,
the flip-flop chosen can be either positive or negative edge triggered
and you'll get the correct result.

The example circuit but with the inverted clock fed to FF #1 results in:

JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (rising edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (rising edge)
10 01 0 0 -- after fourth clock (falling edge)

And we have a quadrature divide-by-two.

Enjoy!

Lyle KK7P





Yahoo! Groups Links

Cecil Bayona
KD5NWA
www.qrpradio.com

Cecil,

Why not use 50% clock phases staggered by 90 degrees? If you also have non-inverted and inverted RF, as in Softrock40, you can then get the equivalent of "full wave rectification" with two SPDT switches. This will give more output than 25% phases which result in "half wave rectification".

Milt,
W8NUE


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That is what they are using in the new SR-5, two clocks staggered at 90 degrees.

You can use a 50% quadrature but it doesn't seem to work as good as the two 25% added together. Some of the guys are doing research into that, and the results so far is that the output is the best when the clocks are slightly less than 25% of the period.

A QSD though is not a rectifier but a sampling integrator which are not quite the same.

At 11:22 AM 10/28/2005, you wrote:

KD5NWA wrote:

That is the problem with /2 quadrature generation, you need a
symmetrical input clock so you can use both edges to the clock. That
is, if you are going to 25% clock phases for maximum gain. You can
use a clock at less that the frequency of interest (sub-sampling) but
your gain goes down.

If you have a symmetrical 2X clock you might as well use a doubler
(analog or digital) and divide by 4 to get a 25% clock phase.


At 10:22 AM 10/28/2005, you wrote:

Here is the file again. I did not post it to the files section.

I was

referring to the 74HC and 74AHC, high speed and advanced high

speed CMOS.

I'm probably working through the truth tables incorrectly, but I don't
think this is a quadrature divide-by-2. It appears to be a quadrature
divide-by-four.

Call the upper FF #1 and the lower FF #2, use the indicated 74xx73 which
has a negative-edge-triggered clock, and have both reset as the initial
condition, then:

JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (falling edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (falling edge)
10 01 0 0 -- after fourth clock (falling edge)

We are now back to the initial condition and the cycle repeats ad

infinitum.

To get a quadrature divide by two, you need to toggle one flip-flop on
the positive edge of the clock, and the other on the negative edge of
the clock, as there are only a total of 4 edges in a 2x clock. This
also implies the clock must be perfectly symmetrical, e.g. a 50% duty

cycle.

If this is the case, you can use a D (with input tied to its own /Q), a
J-K (with J and K both pulled high) or a T flip-flop, and run the clock
through an exclusive-OR to each of the two flip-flop clock inputs. One
Ex-Or will have its second input pulled high, the other pulled low, so
you have a clock and its inverse with essentially equal delay. Thus,
the flip-flop chosen can be either positive or negative edge triggered
and you'll get the correct result.

The example circuit but with the inverted clock fed to FF #1 results in:

JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (rising edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (rising edge)
10 01 0 0 -- after fourth clock (falling edge)

And we have a quadrature divide-by-two.

Enjoy!

Lyle KK7P





Yahoo! Groups Links

Cecil Bayona
KD5NWA
www.qrpradio.com

Cecil,

Why not use 50% clock phases staggered by 90 degrees? If you also have
non-inverted and inverted RF, as in Softrock40, you can then get the
equivalent of "full wave rectification" with two SPDT switches. This
will give more output than 25% phases which result in "half wave
rectification".

Milt,
W8NUE


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Version: 7.1.362 / Virus Database: 267.12.5/150 - Release Date: 10/27/2005





Yahoo! Groups Links

Cecil Bayona
KD5NWA
www.qrpradio.com

I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ...

KD5NWA wrote:

That is what they are using in the new SR-5, two clocks staggered at
90 degrees.

You can use a 50% quadrature but it doesn't seem to work as good as
the two 25% added together. Some of the guys are doing research into
that, and the results so far is that the output is the best when the
clocks are slightly less than 25% of the period.

A QSD though is not a rectifier but a sampling integrator which are
not quite the same.

Cecil,

If the QSD is a sampling INTEGRATOR, would the 50% period integrator not give the maximum value? Integrating a sine wave over one half cycle gives the maximum output. A shorter, or longer, period will give less than 2/PI.

If you use a sample and hold, obviously sampling at the peaks give the maximum value. This would imply a very short sampling interval.

If you use a track and hold, the signal would be maximum at the end of the sample interval.

The Softrock40 appears to be something between an integrator and the sample and hold.

I am using a 50% sampling interval with 2 DDSs for a PSK31 application. I get maximum output with the 50% sampling interval, with an RC integrator at the output of the switches. 25% sampling results in 6dB less signal.

Milt
W8NUE


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A simple test can be made with the v4.0 SoftRock of this four switch QSD concept. All necessary signals are at pads of U4 loaction as well as the switch control lines. All that needs to be done is to remove U4 and put in the appropriate jumpers between various pads of the U4 location. I will be building another v4.0 SoftRock this weekend and I will try that experiment.

73,
Tony KB9YIG

It seems that we agree more than originally anticipated in this discussion, I agree the SoftRock design is not quite a integrator, the capacitor follows the signal too closely, not enough impedance on the circuit feeding the cap.

I would be almost willing to bet that your circuit is set with the transformer having a high impedance and larger resistors so it is closer to a integrator, in which case 50% is optimum.

They are setting the SoftRock series with very low impedance into the capacitor so it's closer to a sample and hold, that's why a 15% to 20% signal is optimum.

I would tend to believe that the current SR-40 scheme and the 2X scheme would give close to the same result.

The previous scheme uses a slower speed 2X clock that must be symmetrical with two capacitors, theirs a 4X clock that doesn't care about symmetry and four capacitors. With 2X scheme you can still use four capacitors and add the results and end up with a better signal to noise ratio.

Interesting thought, maybe a run through Spice would be worthwhile, it would not be that difficult to model and compare the different schemes before I finalize my design.

I'm at work right now, and I'm bored out of my mind, they are doing inventory, and I just sit by the accountants in case there is computer or mainframe problems, which has never occurred. My heavy part of the work was yesterday setting up all the computers needed. But I don't have a working Spice software in my PC, I forgot at 4:30 AM to pickup the CD's so I could install the software. I'll look for a freebie visual version that I tried before, if I can remember the name, Symmetrix? or something like that.


At 12:22 PM 10/28/2005, you wrote:

KD5NWA wrote:

That is what they are using in the new SR-5, two clocks staggered at
90 degrees.

You can use a 50% quadrature but it doesn't seem to work as good as
the two 25% added together. Some of the guys are doing research into
that, and the results so far is that the output is the best when the
clocks are slightly less than 25% of the period.

A QSD though is not a rectifier but a sampling integrator which are
not quite the same.

Cecil,

If the QSD is a sampling INTEGRATOR, would the 50% period integrator not
give the maximum value? Integrating a sine wave over one half cycle
gives the maximum output. A shorter, or longer, period will give less
than 2/PI.

If you use a sample and hold, obviously sampling at the peaks give the
maximum value. This would imply a very short sampling interval.

If you use a track and hold, the signal would be maximum at the end of
the sample interval.

The Softrock40 appears to be something between an integrator and the
sample and hold.

I am using a 50% sampling interval with 2 DDSs for a PSK31 application.
I get maximum output with the 50% sampling interval, with an RC
integrator at the output of the switches. 25% sampling results in 6dB
less signal.

Milt
W8NUE


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Checked by AVG Free Edition.
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Yahoo! Groups Links

Cecil Bayona
KD5NWA
www.qrpradio.com

I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ...

Milt,

If it needs a symmetrical clock, I would recommend the sine wave to square wave converter used in the QRP2001 RF section. It just takes one gate, in this case it is an exclusive OR gate, but it can be two NAND gates, or anything similar as well. Just feed back some of the output to the input through a resistive T network with a shunt capacitor to ground in the middle to filter the RF. This bias feedback arrangement will square up any sine wave. It is commonly used by high speed logic designers to square up their clocks to obtain maximum frequency capability of their logic circuits.

As an RF engineer I used one of these circuits as a high frequency phase stable frequency multiplier about 26 years ago. It used, I think, two ECL 1663 NOR gates which at that time were pretty fast. The sine wave input was at 50 MHz. All I had to do to "tune" it was to look at the output on a spectrum analuyzer and set one of the resistor values for minimum output on the even harmonics. I could get about 30 dB even harmonic rejection over quite a wide frequency range compared to the odd harmonics which are what make up a 50% duty cycle square wave. (Then it was also easier to filter the output signal I wanted at 350 MHz., which is an odd harmonic, since the even harmonics on either side were greatly attenuated. And it had spectacular phase stability, because all devices were differential inputs on the same die, so they were temperature matched as well.)

Anyhow, it was an easy way to get a symmetric clock. I think it would work for the JK Flip Flop method as well.

Bill

Milt Cram wrote: