Kees,
Here is the file again. I did not post it to the files section. I was referring to the 74HC and 74AHC, high speed and advanced high speed CMOS.
Bill
KY1K wrote:
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At 10:34 PM 10/27/2005, you wrote:
Kees,
It would seem to me that two JK flip flops followed by 4 exclusive OR
gates to get the 0 and 180 degree shifts, would be a great way to
minimize the component costs and still be able to divide by 2 and get
the four outputs you need for a four switched capacitor Tayloe
detector. And you wouldn't lose any gain, which is kind of important in
a receiver like this for lowest noise performance. And it would only
take 2 chips total.
The exclusive OR gates would maintain the same delay with the 0 and 180
degree shifts as well as the 90 and 270 degree shifts. Just tie the
unused input of each gate to either gnd or +5 to shift either 0 or 180
degrees.
The JK flip flop schematic I posted earlier seems to be the most
symmetric way of getting the 0 and 90 degree shift to start with.
But I also notice that no one makes JK flip flops anymore, at least for
the high speed CMOS stuff. I don't know why...
Hi Bill,
Maybe my memory has failed, but I think I had little difficulty
finding a JK, think it was a 74AC109. I'm not sure why they would
fall out of popularity unless there is something that is inherently
slower due to the design. I think ANND gates are always faster than
AND gates, which is why we see more types of NAND gates for example.
I missed your posting of the schematic, if you still have it, can you
email it please.
Thanks,
Art
Maybe someone else knows?
Bill
windy10605@... wrote:
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