Here is the file again. I did not post it to the files section. I was referring to the 74HC and 74AHC, high speed and advanced high speed CMOS.
I'm probably working through the truth tables incorrectly, but I don't think this is a quadrature divide-by-2. It appears to be a quadrature divide-by-four.
Call the upper FF #1 and the lower FF #2, use the indicated 74xx73 which has a negative-edge-triggered clock, and have both reset as the initial condition, then:
JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (falling edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (falling edge)
10 01 0 0 -- after fourth clock (falling edge)
We are now back to the initial condition and the cycle repeats ad infinitum.
To get a quadrature divide by two, you need to toggle one flip-flop on the positive edge of the clock, and the other on the negative edge of the clock, as there are only a total of 4 edges in a 2x clock. This also implies the clock must be perfectly symmetrical, e.g. a 50% duty cycle.
If this is the case, you can use a D (with input tied to its own /Q), a J-K (with J and K both pulled high) or a T flip-flop, and run the clock through an exclusive-OR to each of the two flip-flop clock inputs. One Ex-Or will have its second input pulled high, the other pulled low, so you have a clock and its inverse with essentially equal delay. Thus, the flip-flop chosen can be either positive or negative edge triggered and you'll get the correct result.
The example circuit but with the inverted clock fed to FF #1 results in:
JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (rising edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (rising edge)
10 01 0 0 -- after fourth clock (falling edge)
And we have a quadrature divide-by-two.
Enjoy!
Lyle KK7P
