|
Kees,
toggle quoted message
Show quoted text
It would seem to me that two JK flip flops followed by 4 exclusive OR gates to get the 0 and 180 degree shifts, would be a great way to minimize the component costs and still be able to divide by 2 and get the four outputs you need for a four switched capacitor Tayloe detector. And you wouldn't lose any gain, which is kind of important in a receiver like this for lowest noise performance. And it would only take 2 chips total. The exclusive OR gates would maintain the same delay with the 0 and 180 degree shifts as well as the 90 and 270 degree shifts. Just tie the unused input of each gate to either gnd or +5 to shift either 0 or 180 degrees. The JK flip flop schematic I posted earlier seems to be the most symmetric way of getting the 0 and 90 degree shift to start with. But I also notice that no one makes JK flip flops anymore, at least for the high speed CMOS stuff. I don't know why... Maybe someone else knows? Bill windy10605@... wrote: John,Here's my understanding of the I and Q representation. You have toThere is a difference between "sample at four times the desired |
