开云体育

That is what they are using in the new SR-5, two clocks staggered at
90 degrees.

You can use a 50% quadrature but it doesn't seem to work as good as
the two 25% added together. Some of the guys are doing research into
that, and the results so far is that the output is the best when the
clocks are slightly less than 25% of the period.

A QSD though is not a rectifier but a sampling integrator which are
not quite the same.

At 11:22 AM 10/28/2005, you wrote:

KD5NWA wrote:

That is the problem with /2 quadrature generation, you need a
symmetrical input clock so you can use both edges to the clock. That
is, if you are going to 25% clock phases for maximum gain. You can
use a clock at less that the frequency of interest (sub-sampling) but
your gain goes down.

If you have a symmetrical 2X clock you might as well use a doubler
(analog or digital) and divide by 4 to get a 25% clock phase.


At 10:22 AM 10/28/2005, you wrote:

Here is the file again. I did not post it to the files section.

I was

referring to the 74HC and 74AHC, high speed and advanced high

speed CMOS.

I'm probably working through the truth tables incorrectly, but I don't
think this is a quadrature divide-by-2. It appears to be a quadrature
divide-by-four.

Call the upper FF #1 and the lower FF #2, use the indicated 74xx73 which
has a negative-edge-triggered clock, and have both reset as the initial
condition, then:

JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (falling edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (falling edge)
10 01 0 0 -- after fourth clock (falling edge)

We are now back to the initial condition and the cycle repeats ad

infinitum.

To get a quadrature divide by two, you need to toggle one flip-flop on
the positive edge of the clock, and the other on the negative edge of
the clock, as there are only a total of 4 edges in a 2x clock. This
also implies the clock must be perfectly symmetrical, e.g. a 50% duty

cycle.

If this is the case, you can use a D (with input tied to its own /Q), a
J-K (with J and K both pulled high) or a T flip-flop, and run the clock
through an exclusive-OR to each of the two flip-flop clock inputs. One
Ex-Or will have its second input pulled high, the other pulled low, so
you have a clock and its inverse with essentially equal delay. Thus,
the flip-flop chosen can be either positive or negative edge triggered
and you'll get the correct result.

The example circuit but with the inverted clock fed to FF #1 results in:

JK1 JK2 Q1 Q2
10 01 0 0 -- initial condition
10 10 1 0 -- after first clock (rising edge)
01 10 1 1 -- after second clock (falling edge)
01 01 0 1 -- after third clock (rising edge)
10 01 0 0 -- after fourth clock (falling edge)

And we have a quadrature divide-by-two.

Enjoy!

Lyle KK7P





Yahoo! Groups Links

Cecil Bayona
KD5NWA
www.qrpradio.com

Cecil,

Why not use 50% clock phases staggered by 90 degrees? If you also have
non-inverted and inverted RF, as in Softrock40, you can then get the
equivalent of "full wave rectification" with two SPDT switches. This
will give more output than 25% phases which result in "half wave
rectification".

Milt,
W8NUE


--
No virus found in this outgoing message.
Checked by AVG Free Edition.
Version: 7.1.362 / Virus Database: 267.12.5/150 - Release Date: 10/27/2005





Yahoo! Groups Links

Cecil Bayona
KD5NWA
www.qrpradio.com

I fail to see why doing the same thing over and over and getting the
same results every time is insanity: I've almost proved it isn't;
only a few more tests now and I'm sure results will differ this time ...






Yahoo! Groups Links