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Tony, Cecil, et al Would you fellows agree that this Spice model is a reasonable representation of the switching circuit in the Softrock40? Screenshot of Spice Model The output is taken across the

I did a rough approximation, and using a SPDT switch into a capacitor increase the signal by 50% versus a single switch, using two caps and two independent switches increases it by 100% when you add

It seems that we agree more than originally anticipated in this discussion, I agree the SoftRock design is not quite a integrator, the capacitor follows the signal too closely, not enough impedance on

Hi Phil, 25% does not seem to be a magical number. I changed R1,R2,R6 and R7 in the original model from 200 to 100 Ohms, and the optimal on-time changed to17%. 73 Alex VE3NEA

A simple test can be made with the v4.0 SoftRock of this four switch QSD concept. All necessary signals are at pads of U4 loaction as well as the switch control lines. All that needs to be done is to

KD5NWA wrote: Cecil, If the QSD is a sampling INTEGRATOR, would the 50% period integrator not give the maximum value? Integrating a sine wave over one half cycle gives the maximum output. A shorter,

That is what they are using in the new SR-5, two clocks staggered at 90 degrees. You can use a 50% quadrature but it doesn't seem to work as good as the two 25% added together. Some of the guys are

KD5NWA wrote:

That is the problem with /2 quadrature generation, you need a symmetrical input clock so you can use both edges to the clock. That is, if you are going to 25% clock phases for maximum gain. You can

I'm probably working through the truth tables incorrectly, but I don't think this is a quadrature divide-by-2. It appears to be a quadrature divide-by-four. Call the upper FF #1 and the lower FF #2,

Phil, I have built a model of the single switch mixer and get the same result. The conversion loss is lowest when the on time is 25%. I'm curently working on a mathematical model of the mixer to

Thanks for the input Bill, I'll look into it. 73 Kees K5BCQ ---------- Forwarded Message ---------- Kees, It would seem to me that two JK flip flops followed by 4 exclusive OR gates to get the 0 and

Sounds good so far, Tony. How about a picture? -Bruce N1RX

Kees, Here is the file again. I did not post it to the files section. I was referring to the 74HC and 74AHC, high speed and advanced high speed CMOS. Bill KY1K wrote:

Good Morning All, The first example of the SoftRock v5.0 is now playing nicely. I received the boards on Thursday and was able to finish the build a little after midnight, early Friday morning. No

Hi Bil

Kees, It would seem to me that two JK flip flops followed by 4 exclusive OR gates to get the 0 and 180 degree shifts, would be a great way to minimize the component costs and still be able to divide

John, There is a difference between "sample at four times the desired carrier" 4X the frequency and "sample four times during the desired carrier cycle" (90,180,270, and 360) which can be done with a

Thanks, should not steps 1 and 2 be switched for maximum accuracy?