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Re: Offset adjust to compensate for pad spacing error in fine pitch components.
JPD Borgna
开云体育JPD Borgna wrote:Has any one made a board with this and solder it right???? please! if not, i have to call my manufacturer right now toyajeed2000 wrote: stop the making of my board! Saludos, Juan Pablo. Hi, I forgot to mention that I'm using a 20x Binocular microscope to check the alignment of the pins,if that makes any difference. David.Well, the pins are not perfect (all in the center of the pad) but all of them appear to be good. The poscript you send is a file->print or its a plot printed? Saludos, Juan Pablo. -- Juan Pablo Daniel Borgna -- Técnico Electrónico INTI-Electrónica e Informática Dirección: Avenida General Paz 5445 entre Albarellos y Constituyentes CC157 (CP B1650KNA) San Martín, Bs. As., Argentina TE:+(5411)4724-6200 |
Re: Offset adjust to compensate for pad spacing error in fine pitch components.
yajeed2000
I'm just using the file -> plot dialogue using the windows version of
kicad.I will try to print it out using Linux over the weekend, to see if it makes any difference. --- In kicad-users@..., JPD Borgna <jpborgna@i...> wrote: check all ofthe alignment of the pins,if that makes any difference.Well, the pins are not perfect (all in the center of the pad) but them appear to be good.Constituyentes CC157 (CP B1650KNA) San Martín, Bs. As., Argentina TE:+(5411)4724-6200 |
Re: Offset adjust to compensate for pad spacing error in fine pitch components.
JPD Borgna
yajeed2000 wrote:
Hi,Well, the pins are not perfect (all in the center of the pad) but all of them appear to be good. The poscript you send is a file->print or its a plot printed? Saludos, Juan Pablo. -- Juan Pablo Daniel Borgna -- Tcnico Electrnico INTI-Electrnica e Informtica Direccin: Avenida General Paz 5445 entre Albarellos y Constituyentes CC157 (CP B1650KNA) San Martn, Bs. As., Argentina TE:+(5411)4724-6200 |
Re: Offset adjust to compensate for pad spacing error in fine pitch components.
JPD Borgna
开云体育yajeed2000 wrote:Hi there!Hi, I've uploaded it to the test print plot folder. I've been using Ghostview to veiw and print the files to a HP laserjet colour printer (a new one at work, so its not worn out). Can people please try this file and let me know if it has the same problem. Ive printed it with a lexmark laser printer using linux and ghostview and put my spartan2-pq208 on top of the printed page and (with a magnifiying glass) saw that the pads are OK! Im interesed in this tests too because ive just send my board (wich uses? this) to the factory for made some prototypes. If any one else can test them, please!! Saludos, Juan Pablo. Thanks, David. --- In kicad-users@..., Ian bell wrote:yajeed2000 wrote:Hi, I am trying to print out several square 28 x 28 208 pin quad flat packages using a standard laser printer. However when printed the pads do not line correctly with actual component pins.There is a small error in the spacing of the pinsthatis caused either by the printer (paper stretch)or in Kicad. It would be useful if some kind of VERY SMALL offset adjustment(X andY direction)could be introduced in the print dialog. Alternatively could anyone suggest a way of correcting this error. Thanks. DavidCould you post a copy of one that has this problem to the files section of the group? That way others can try rpinting it see if itisjust a problem at your end or a general Kicad problem. Ian -- Ian T-Bell aka RuffRecords aka RedTommo------------------------ Yahoo! Groups Sponsor --------------------~--> Get Bzzzy! (real tools to help you find a job). Welcome to the Sweet Life. --------------------------------------------------------------------~-> Please contribute your symbols and modules to the library folder in the group files section. Yahoo! Groups Links <*> To visit your group on the web, go to: <*> To unsubscribe from this group, send an email to: kicad-users-unsubscribe@... <*> Your use of Yahoo! Groups is subject to: -- Juan Pablo Daniel Borgna -- Técnico Electrónico INTI-Electrónica e Informática Dirección: Avenida General Paz 5445 entre Albarellos y Constituyentes CC157 (CP B1650KNA) San Martín, Bs. As., Argentina TE:+(5411)4724-6200 |
Re: Offset adjust to compensate for pad spacing error in fine pitch components.
yajeed2000
Hi,
I've uploaded it to the test print plot folder. I've been using Ghostview to veiw and print the files to a HP laserjet colour printer (a new one at work, so its not worn out). Can people please try this file and let me know if it has the same problem. Thanks, David. --- In kicad-users@..., Ian bell <ianbell@u...> wrote: that (X andis caused either by the printer (paper stretch)or in Kicad. isY direction)could be introduced in the print dialog.Could you post a copy of one that has this problem to the files just a problem at your end or a general Kicad problem. |
New file uploaded to kicad-users
Hello,
This email message is a notification to let you know that a file has been uploaded to the Files area of the kicad-users group. File : /Print Plot Tests/PQFP208-SoldPCmp.ps Uploaded by : yajeed2000 <djsbriscoe@...> Description : 28X28 208 pin QFP pins don't line up with device. You can access this file at the URL: To learn more about file sharing for your group, please visit: Regards, yajeed2000 <djsbriscoe@...> |
Re: Offset adjust to compensate for pad spacing error in fine pitch components.
Ian bell
yajeed2000 wrote:
Hi,Could you post a copy of one that has this problem to the files section of the group? That way others can try rpinting it see if it is just a problem at your end or a general Kicad problem. Ian -- Ian T-Bell aka RuffRecords aka RedTommo www.geocities.com/ruffrecords |
Offset adjust to compensate for pad spacing error in fine pitch components.
yajeed2000
Hi,
I am trying to print out several square 28 x 28 208 pin quad flat packages using a standard laser printer. However when printed the pads do not line correctly with actual component pins.There is a small error in the spacing of the pins that is caused either by the printer (paper stretch)or in Kicad. It would be useful if some kind of VERY SMALL offset adjustment (X and Y direction)could be introduced in the print dialog. Alternatively could anyone suggest a way of correcting this error. Thanks. David |
Re: Vias on zones
fluissman
Hi,
1st - Select the option 'Add wire or via' 2nd - Go to the place of the zone where you want to put de via. Left click. 3rd - Without moving the mouse, right click and select 'Add via' 4th - Without moving the mouse, right click again and select 'End of wire'. Then you have the via... I've made a translation from Spanish of the options. Maybe in English version are different.... bye --- In kicad-users@..., Pedro Martín del Valle <pmartin@p...> wrote: the other one on the copper layer, using vias. |
Re: Vias on zones
Pedro Martín del Valle
Thanks to everyone who has asked my question.
toggle quoted message
Show quoted text
I had missed to click with the left button on the zone before clicking with the rigth button to add the via. Pedro. JPD Borgna wrote:To attach the zone to a net, you have to first highlight the net withyou are right, I wasn't thinking. I actually did have the zone connected |
Re: Creating BOM in Kicad
Ian bell
hmistry494 wrote:
Hello guys i am an Orcad 386 plus user and i am experimenting withAFAIK this is not possible at present. You can add values in additional fields of a component such as price or part number but I don not think it is possible yet to select these into the BOM. Ian -- Ian T-Bell aka RuffRecords aka RedTommo www.geocities.com/ruffrecords |
Re: Vias on zones
ryan williams
JPD Borgna wrote:
To attach the zone to a net, you have to first highlight the net with "Resaltar Red", then create the zone.you are right, I wasn't thinking. I actually did have the zone connected to ground. that is why it worked in the end. But, DRC does not recognize the connections unless an actual trace starts from each ground pad, and ends at another. To clarify, a picture of the board is here:It would be good to have the posibility, but dont know if that is right at the design of a pcb (to put thermals in a thruhole). I wanted thermals on the vias because it is a pain to solder (if you don't have soldermask). You can see there, that ground pads of each module have thermals, but the vias do not. My professor actually commented on my lack of thermals on the vias. -ryan |
Re: Vias on zones
JPD Borgna
开云体育ryan williams wrote:To attach the zone to a net, you have to first highlight the net with "Resaltar Red", then create the zone.Pedro Martn del Valle wrote:I am trying to connect 2 GND-zones, one on the components layer and the other one on the copper layer, using vias. Can anyone tell me how to put this vias? Is there a way to attach a zone with a net? I did the same thing. I been told that in some commercial programs you have to do the same. Dont know.I'm not sure if there is a good way to do it. I just built a board that needed this. I ended up drawing actual traces between all of the grounds. When the board is actually made, you can't tell the difference. It would be good to have the posibility, but dont know if that is right at the design of a pcb (to put thermals in a thruhole).if you are willing to accept many DRC errors, then you could just draw a few small traces of the ground pads and add VIAs. I would suggest that a "connect to net" box be added to the zone file dialog, and the fill zones should be a part of the DRC. Another problem I have is the inability to use thermals around the vias on the ground plane. Saludos, Juan Pablo. -ryan -- Juan Pablo Daniel Borgna -- Tcnico Electrnico INTI-Electrnica e Informtica Direccin: Avenida General Paz 5445 entre Albarellos y Constituyentes CC157 (CP B1650KNA) San Martn, Bs. As., Argentina TE:+(5411)4724-6200 |
Re: Vias on zones
fluissman
hi...
thanks Manuel, and sorry again fernando --- In kicad-users@..., Manuel Jimenez <pafbat00@y...> wrote: a la componentes y ------------------------------------------------------------------------ <mailto:kicad-users-unsubscribe@...?subject=Unsubscribe>YAHOO! GROUPS LINKS ------------------------------------------------------------------------ ------------------------------------------------------------------------01/11/2005 |
Re: Vias on zones
ryan williams
Pedro Martn del Valle wrote:
I am trying to connect 2 GND-zones, one on the components layer and the other one on the copper layer, using vias.I'm not sure if there is a good way to do it. I just built a board that needed this. I ended up drawing actual traces between all of the grounds. When the board is actually made, you can't tell the difference. if you are willing to accept many DRC errors, then you could just draw a few small traces of the ground pads and add VIAs. I would suggest that a "connect to net" box be added to the zone file dialog, and the fill zones should be a part of the DRC. Another problem I have is the inability to use thermals around the vias on the ground plane. -ryan |
Re: Vias on zones
Manuel Jimenez
开云体育TRANSLATION:Tonamiben wrote: (Pafbat did translate) Hi Peter, >when you put the via with 'Add wire or via' option, right click > tecla derecha del raton y una de las opciones es 'Seleccionar par deand select 'Select couple of layers > capas para las vias'. Precisamente te da a escoger la de componentes yfor vias'. It offers you the posibility of taking the components one > la de cobre... espero que sea esto lo que preguntas...and the copper oner... I hope this was what you asked... > |
Re: Vias on zones
Tonamiben
fluissman wrote:
My english is not very good too, but it would be very interresting to see what you reply and what was the solution you propose. Benoit |
Re: Vias on zones
fluissman
Hola Pedro,
cuando colocas la via con la opcion 'A?adir pista o via', le das a la tecla derecha del raton y una de las opciones es 'Seleccionar par de capas para las vias'. Precisamente te da a escoger la de componentes y la de cobre... espero que sea esto lo que preguntas... un saludo.... por cierto, la traduccion esta de PM... Sorry for all the rest... but my English is not very good... bye Fernando --- In kicad-users@..., Pedro Martín del Valle <pmartin@p...> wrote: the other one on the copper layer, using vias. |
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