Hi Albin,
I'm afraid KiCad is not yet aware of pad-stacks. The pad will be
present on all your internal layers, and so the DRC is correctly
warning you of the violation.
It is best to plot one of the inner layers and view it with the gerber
viewer, you'll see that the TH pad is present on this layer.
Because a pad-stack cannot be defined in KiCad, a pad is either on one
of the outer layers (SMT) or on all layers (TH).
Good luck with your project.
Best Regards,
Brian.
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On 27 January 2011 13:15, dennevi <dennevi@...> wrote:
Hi
I have a six layer PCB with a connector using plated-through-hole mounting and would like to run traces between the holes in layer 2-5. In layer 1 and 6 the pads are to close to each other but in the inner layer it shouldn't be a problem.
It seems however that I'm unable to do so without complaints from the DRC.
Is it supposed to be like this? Do the pads need to be the same size in the inner layers?
What's the best way to get around this?
I guess I could route the traces with DRC turned off, but I'm not happy with this since the over all DRC will fail later.
I also believe I could get around this by creating one round drilled pad in layer 1 and another similar pad i layer 6 with the exact same position and pin-number. I haven't tried yet though. Is there any better way to do this, or shouldn't I even try to do this?
Kind regards
Albin, Sweden
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