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Crystal oscillator oscillation startup
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Here is an initial circuit draft of a crystal oscillator :?ck_osc.zip ? ? ? ? ??
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I have so far checked the circuit operating points according to the circuit requirements.
However, it just does not start to oscillate.
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I am a circuit beginner noob, please feel free to point out mistakes and guide me to solve the oscillation startup issue. |
¿ªÔÆÌåÓýThere are variety of problems that need fixing first, most importantly: all your N channel? devices are upside-down. I don't actually see a crystal in your schematic, but that's secondary.My advice is to start small. Make an inverter. Test it - does it work? Have you tested any part of this schematic? If this is your first attempt, you stand zero chance of drawing it all out and having it to work first time. --
Regards, Tony On 02/05/2025 15:20, Cheng Fei Phung
via groups.io wrote:
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On Fri, May 2, 2025 at 09:20 AM, Cheng Fei Phung wrote:
Umm, your simulation is a .DC sweep.? .DC sweeps can't oscillate.
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Where is the crystal?? Nothing stands out as being the crystal.? If it is there, I apologize.? Please help us by pointing it out.
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Did you upload the wrong schematic by accident?
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When you get to the point of running .TRAN simulations, try it first with .TRAN ... STARTUP and a very long simulation time (10 or 1000 seconds instead of 10 microseconds).? If that doesn't work, then try .TRAN ... UIC.? If it still won't oscillate, try adding specific sources of transients (PULSE sources) into the circuit, to kick-start it.? But first I think you need to add a crystal, and make sure that it has good parameters for a high-Q crystal.
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Andy
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@Tony
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The upside-down issue is due to how mosfet_018.lib had been defined, please note that both PM and NM from this lib file had been verified previously.
See also /g/LTspice/photo/302220/3911530 |
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On Fri, May 2, 2025 at 12:59 PM, Cheng Fei Phung wrote:
I think that is unlikely.? It is a schematic drawing issue, not a model one.? MOSFETs are normally used where the N-channel current flow is into the Drain pin, through the channel, and out the Source pin.? But your N-channel MOSFETs are drawn upside-down, forcing positive channel current to flow backwards, from Source to Drain.? I do not think that their SPICE model definition can alter that; the physical arrangement of the transistor's internals would be all wrong.? All SPICE FET models using .MODEL statements are meant to use the pin-order D-G-S-B.? You have hooked your circuit to the wrong pins.
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Two other things to note:
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You might have used the models not the way they were intended.? The model file (mosfet_018.lib) defines both .MODEL models and .SUBCKT models, where the only difference is that the .SUBCKTs come with built-in formulas for AS, AD, PS, and PD.? But your schematic uses the .MODEL models, which means they do not pass values for AS, AD, PS, or PD to those transistors from their .SUBCKT definitions.? That's OK, if that is what you intended.? Just be aware that all of your MOSFETs default to AS=0, AD=0, PS=0, and PD=0 because your transistor symbols did not specify values for those parameters.
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Also, I see that some of your transistors might connect their Bulk pins to the wrong? place.? Looking at M19, M17, M9, M37, M39, M5, M22, M33, and M35, their Bulk pins connect to internal circuit nodes between the supply voltages.? That is probably not how those transistors are built (on the die), so those connections are probably incorrect.? Normally, MOSFET Bulk pins should connect to either VSS (for N-channel) or VDD (for P-channel) and to nothing else - with very few exceptions.? I am not a fabrication expert but I would expect that additional wafer processing steps are required to connect those pins to any other net.
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Andy
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On Fri, May 2, 2025 at 01:22 PM, Cheng Fei Phung wrote:
I think you are missing the crystal.? Where is the crystal? ?
Is this really a crystal oscillator?? Or is it a relaxation oscillator without a crystal?
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What determines the oscillator's frequency?
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Andy
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Re: the upside-down N-channel MOSFETs -
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It should also be noted that many MOSFETs are symmetrical, where Source and Drain are electrically interchangeable.
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Even when that is true, I think it would be wise to draw the schematic correctly, so that the symbol's Source pin is actually used as a Source pin, and not used as a Drain pin.? The way you drew it, you used the Source as the Drain, and you used the Drain as the Source.? It might not alter its performance but the schematic is incorrect in that regard.
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I do not think there is any reason why those FETs needed to be drawn upside-down.
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Andy
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On Fri, May 2, 2025 at 12:59 PM, Cheng Fei Phung wrote:
In that photograph, which is a picture of a schematic drawn in a different program (not LTspice), it shows that the N-channel Source pins are lower down on the page.? ?That differs from how you drew them in LTspice.? In your schematic, the N-channel MOSFET Source pins are higher up.? They are indeed backwards (upside-down) compared to the schematic you tried to replicate. ?
In LTspice's version of the MOSFET symbol, the Source pin is the one horizontally adjacent to the Gate pin, for both N and P channel types.
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With LTspice's version of the MOSFET symbols, one normally needs to rotate the P-channel symbols to make its Source pin higher up on the schematic - assuming that your schematic has the positive supply voltage up and the negative supply voltage down.? But the N-channel symbols should not be rotated.? They are already oriented correctly.
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It is unfortunate that there are multiple "standards" for MOSFET symbols.
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Andy
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I do not see a crystal on the schematic photo you uploaded (/g/LTspice/photo/302220/3911530).
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I wonder if that schematic is supposed to be just the on-chip part of a circuit, where you are supposed to connect a crystal externally, perhaps to the "Q1" and "Q2" pins.? But I think you have not done that.? Without a crystal connected, it might never oscillate.
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The other two screenshots you uploaded show somewhat small time scales.? You may need to start with simulations lasting hundreds of seconds or more, until you get something to happen.? In one of the photos, a voltage or a current is still changing even at 10 seconds, so clearly the circuit has not stabilized yet.? This does not mean that it will start oscillating if allowed to run longer, but it is possible.? If waveforms are still changing up to the end of your simulation, you have not waited long enough.
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In this case, I suspect that "waiting long enough" will not fix it.? I suspect the missing crystal is a critical deficiency.
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Andy
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@Andy
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still do not show any oscillatory phenomenon after adding RLC between Q1 and Q2.
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See?ck_osc.asc for the latest asc file |
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On Fri, May 2, 2025 at 09:02 PM, Cheng Fei Phung wrote:
I see you added a simple RLC series resonant circuit to represent a crystal.? Do you know that it is an appropriate model?? Does this oscillator circuit depend on series resonance, or parallel?? (I don't know; I am just asking.)? Are the electrical characteristics OK to model the motional parameters of the crystal? ?
Glancing at the IEEE article, it looks like they used a much more complex electrical model for the crystal, with not one or two but three series resonant RLC circuits in parallel with each other, plus three additional capacitors.? Your equivalent circuit is much simpler.? Is the simpler model adequate?
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The .tran statement on your schematic is ".tran 0 10 0 100u startup", so it calls for a Maximum Timestep of 100 us.? With a timestep of 100 us, it can simulate signals with frequencies up to about 5 kHz.? But your crystal model's series resonance is around 1.1 MHz.? To simulate a circuit oscillating at 1.1 MHz requires a timiestep that is smaller than 500 ns.? There is a chance that you made the Maximum Timestep so large that LTspice is incapable of seeing any sort of oscillation around 1 MHz.
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This is where simulations can become very difficult.? With a timestep smaller than 500 ns, it can take a very long time to simulate 10 seconds or 1000 seconds.
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Your N channel transistors are still upside-down, and the Bulk pins of many of the transistors are likely connected wrongly.? Also you have zero values for PS, PD, AS, and AD, which is technically incorrect, but I don't know how much difference it makes.? As you probably know already, I1 should not be there, but LTspice removes it.
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I suspect that your DC voltages are not right.? The negative supply voltage for the first three stages (node V1) is at -1.5 V which might be right.? But the regulated voltage for the output amplifier (node VN) is +1.5 V.? Is that right?? I think it powers the output amplifier with the wrong polarity.? Are you powering that section correctly?
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There is no DC path from node Q1 to ground, which extends to nodes N004 and N005.? LTspice tells you that the nodes float, and it "corrects" for it by adding GFLOAT to one of the nodes.? I think this won't affect the performance of this circuit, but I'm not sure.? GFLOAT will lower the Q of the resonant circuit a little.
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Note I have not read the IEEE article.
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Andy
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You (Cheng Fei Phung) seem to be grasping at straws with pretty minimal understanding. In your situation, I would disconnect the "crystal" and feed a small transient 1.1MHz signal (say a hundred mV ppk or less) through a small capacitor (few 10s of pF). Verify that the amplifier has the expected operating point and has some actual gain at that frequency. Use a reasonable maximum time step (less than 50ns) and let the simulation run more than a few cycles (10 uS or longer). ?
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Once you have an operating amplifier, THEN hook the simulated crystal.
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You might actually learn something if you observe the results fully and carefully! AND you convey those observations back to the list, in good detail. Hint: that report might include a full spice circuit with all the supporting models that either fails to operate or operates with some degree of success.
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Jim
Oregon Research Electronics
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¿ªÔÆÌåÓýOn 03/05/2025 03:02, Cheng Fei Phung
via groups.io wrote:
Did you check the DC conditions on your circuit? Is it biassed correctly? What gain do you get from each inverter? Make one step at a time. To help you (and anyone else following) along the way, I have made some testjigs to validate the characteristics of both P and N devices, including both the normal and inverted N configurations (they are identical, so the devices are symmetrical). See 180nm_Testjigs.zip --
Regards, Tony |
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@Tony
See ck_osc_positive_supply.asc , I had actually checked the operating points conditions for each transistors according to circuit requirements. I am now interpreting the underlying theory, I will get back to you next week with details. |
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On Sat, May 3, 2025 at 05:45 AM, Cheng Fei Phung wrote:
That is a huge change!
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The fact that you moved the ground is insignificant.? It just shifts the voltages.? But you are no longer powering the "VN" net with a voltage source that had the polarity wrong, and that is a significant change.
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Not having studied the IEEE article, I wasn't sure but I suspected that the purpose of the "Output voltage regulator" section (and your M32) was to derive a regulated DC voltage on node VN.? And it looks like that is finally working now, in this schematic.? The earlier schematics you uploaded had that wrong, both by driving VN with a separate voltage source and by giving it the wrong polarity.
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However, I would not expect much difference in circuit performance at this stage.? The oscillator is the part of the circuit way over on the left, and everything else in the schematic is superfluous, except for the DC biasing voltages on nodes "g_a" and "g_b".? The output amplifier is just an output buffer and you could have omitted it because it is not part of the oscillator.? It adds a little load on the "Q1" net but I think that could be mostly ignored.
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What do you hope to achieve by sweeping the supply voltage, V_1?? Does it give you any significant information about the operation of the circuit?? In the end it does, after everything is working.? It tells you about things like supply voltage "pull".? But until the circuit oscillates, I think sweeping V_1 does not give you any useful information.
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I think I might be more interested in sweeping the DC voltage at the input of the oscillator's amplifier (node "M1_gate") and examining what is the transfer function and signal gain of M1.? That gain is what makes the oscillator oscillate - or perhaps why it does not oscillate.? Perhaps you should be looking there.
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That's good - but why have you not considered much of the advice you were given?? It seems to me that you are not very interested in trying to get your circuit right.? Do I read that incorrectly? ?
Andy
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@Andy
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Your advices are valuable and very useful !!! ? Thanks !!!
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> .MODEL statements are meant to use the pin-order D-G-S-B
Got it, noted. I will swap the order and get back to you tomorrow with a corrected circuit.
> at M19, M17, M9, M37, M39, M5, M22, M33, and M35, their Bulk pins connect to internal circuit nodes between the supply voltages I will double check these and get back to you tomorrow with a corrected circuit.
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> Just be aware that all of your MOSFETs default to AS=0, AD=0, PS=0, and PD=0
Noted, is it safe to use 0 for these in your expert opinion ? |
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On Sat, May 3, 2025 at 12:38 PM, Cheng Fei Phung wrote:
"Safe"?? I don't know, it depends on one's definition of "safe". ?
Accurate?? Probably not.? Any time you omit something that you know about, or change a value from what it ought to be, it degrades accuracy.? If I remember right, SPICE MOSFET models include the capacitances of the bottom and sidewalls of the source and drain diffusions.? Leaving them set to 0 removes (ignores) that capacitance.? It might also ignore DC effects from their junction diodes.? Those omissions might be significant or insignificant.
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You might have noticed several warnings about PS and PD in your SPICE Error Logs.
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It is a simple (but tedious) schematic change to switch to the .SUBCKT models which automatically calculate AS, AD, PS, and PD.? Change the Prefix attribute to "X" to use the .SUBCKT version.
? ? Prefix = "X":? call the .SUBCKT model.
? ? Prefix = "MN" or "MP":? call the .MODEL model.
Use Ctrl-right-click to get to LTspice's General Attribute Editor where you can change the Prefix attribute's value.? That must be done to each of your transistors.
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Apparently these models were designed for a fab process with an effective length of 1.1 microns for each Source and Drain diffusion.? Hopefully that is correct.
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Andy
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@Andy
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I have done the three modifications as per your valuable advices.
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May I ask how to resolve the issue for floating node N004 ?
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Note: V004 is between Q1 and the R1 of the series RLC circuit.
Note: The series RLC circuit or Figure 2(b) is an equivalent model of Figure 2(a) inside the IEEE paper.
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Please advise, thanks !!
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Tony Casey
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