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I read Pedro’s comment, and figured he *probably* misunderstood “Time must be monotonically increasing”, which I believe is the case, not Value. Dave Sent: Thursday, May 29, 2025 1:37 PM To:

Can you please say where it is in the Help? I cannot find it, and 'Find keyword' doesn't work. -- This email has been checked for viruses by AVG antivirus software. www.avg.com

If you're wanting to use use digital blocks for a real application, you should note that there are libraries in the LTspice group Files </g/LTspice/files> section for CD4000, 74HC,

I can't guess where you got that information from. What's the point in coming here and asking for help, then rejecting the help you're offered without even trying it? Do you think I didn't try it? --

Hi Andy, After searching for something on Google, look upper-right and click the down arrow next to the tools word. All for now Sent: Thursday, May 29, 2025 at 4:27 PM From: "Andy I via groups.io"

SCOPEDATA=... was introduced precisely for what the OP is trying to do. It provides the legacy behavior. PWL=... will only work for data with montonically increasing x-values. All documented in great

Pedro wrote: I'm afraid that is incorrect. PWL, either with or without "PWL file=", is *not* only for monotonically increasing sources.? Were you taught that?? ?That would be incorrect.? It is for

eewiz wrote: Even Wikipedia ( https://en.wikipedia.org/wiki/Flip-flop_(electronics) ) agrees with "SR latch". Wikipedia is not the authority.? But I would judge it more dependable than Google

Well, it would be IEC rather than ISO. From the IEC Electropedia (free public access), there is: Flip-flop: IEC 60050-702-09-27 monostable trigger circuit The search would have found things like 'S-R

I somewhat disagree with what you wrote. A Google search just gives you search results.? It does not tell you that "'RS latch' is?the?generally accepted term for a set-reset latch."? You can draw

This should not influence you....? But I never understood the purpose of JK flip-flops.? Logically speaking, they are just a little weird.? Maybe there is a place for them but I never understood

It has been corrected already.

The "PWL file" is only for monotonically increasing sources. Since mine is another simulation's export that does not happen. That's why I am using this SCOPEDATA definition. Thanks for the feedback.

Ok the inputs make sense. I will try them, thank you. Sorry for the zip file in the wrong format, I will correct it. Pedro

Hi Andy, No, it's not AI, just search hits. Google will tell you how many times a search term is found on the internet. People wrote RS latch more than 47 million times while SR latch was written some

Why do I get the feeling this is another case where the user uploaded a different schematic than the one they used in their own simulations? As Tony noted, the syntax for the 12 PWL voltage sources is

You got the V-source syntax wrong. Since you're using PWLs defined in files, you need to use the "PWL File" option, not the "PWL (T1,V1,T2,V2...). Just use the Browse button in the PWL File: option.

There is no NIGBT, right?? You have a .MODEL statement for one, but I don't see one on the schematic.? That's OK. I strongly recommend replacing all the diodes with actual diode models.? The SPICE

You forgot to include the data file "data_pulses_svm_SC4.csv.txt".? There should be 12 data files but there are only 11. If I were you, I might start with R24 removed (bottom of V1 grounded) and add

Hi all. Thank you for the feedback. I will study more about all the points that were raised. I had the idea of building a JK flip-flop circuit (after finishing the RS) using digital gates in LTspice,