There is no NIGBT, right?? You have a .MODEL statement for one, but I don't see one on the schematic.? That's OK.

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I strongly recommend replacing all the diodes with actual diode models.? The SPICE default diode "D" lacks any resistance (among other things), and that often leads to convergence problems.? Choose some random diode model instead.? You can even construct a semi-ideal diode using the ".model MyIdealDiode D(Ron=.1 Roff=1Meg Vfwd=.4)" syntax, and it probably behaves 'better' than the default "D" diode.

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Andy

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On Thu, May 29, 2025 at 11:17 AM, <p.dalmeida14@...> wrote:

I honestly have no clue what could be wrong. Can anyone at least point me in the right direction?

You forgot to include the data file "data_pulses_svm_SC4.csv.txt".? There should be 12 data files but there are only 11.

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If I were you, I might start with R24 removed (bottom of V1 grounded) and add it later, after things are working nicely.? I would also start with smaller waveform datafiles until things are working.? And the pulse datafiles need to start at time=0.? By omitting all data from time=0 to time=2, what did you expect the simulation to do for the first two seconds?

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Never, NEVER upload a .7z file.? Please go back and read all of the group's guidelines.? Uploaded compressed/archived files should be .ZIP files only.? A .7z file is not a .ZIP file.

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Andy

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Hi all.

Thank you for the feedback.
I will study more about all the points that were raised.

I had the idea of building a JK flip-flop circuit (after finishing the RS) using digital gates in LTspice, and then using it to control the PWM of my inverter circuit.
But I believe a less labor-intensive path would be to import a model of an integrated circuit into LTspice.
I'll leave the flip-flop construction for another software like LogiSim.

Thanks again.

On Thu, May 29, 2025 at 10:35 AM, eewiz wrote:

According to Google, ...

I have to ask, since I was not aware that Google's search function made such pronouncements.? Does this mean "According to an A.I., ..."?

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I think we know how far we should throw that one.

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Andy

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You are correct, Jim. I’m only now being introduced to this topic in engineering school, so I don’t yet have advanced knowledge. I will study the points you highlighted. Thank you.

On Wed, May 28, 2025 at 09:59 PM, Hawker wrote:

Turns out the last 3 characters are?

0D 0A 1A
so CR/LF/EOF
Removing them works.

The last one (1A = EOF) is the only one that matters to this.? CR/LF are OK.

Does ADI monitor this forum like Linear Tech did?

Some ADI employees are here, but by coincidence and this group is not a means of reporting bugs to them.

This is a major issue to any older TI model so I assume they will figure it out soon soon enough.

Maybe they did already.

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Andy

We used to call them Master/Slave flip-flops, when they had one form of the extra logic to make them edge-triggered.

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Andy

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Turns out the last 3 characters are?

0D 0A 1A
so CR/LF/EOF
Removing them works.

I suspect ADI is aware as I found the fix on an ADI forum from ADI support.
That said I don't know how to file a bug report and not going to take the time to figure it out.? I do miss Helmet, who was good for this on our behalf. Does ADI monitor this forum like Linear Tech did?
This is a major issue to any older TI model so I assume they will figure it out soon soon enough.

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My old stuff like TL07x, TL08x, LM358, LM3904, et all do this but not newer parts like TLV9102, LM358B, OPA1678
Looks like some of my National Semi models (pre TI) have the same issue.

The OP needs to read about flip flops. ?RS flip flops are NOT edge sensitive. They are sensitive to which input is active LAST, Edge sensitive flip flops include D, JK, and others but NOT RS! RS flip flops are often undefined (e.g.. could be anything) if both inputs are active at the same time. The OP needs to understand about active inputs, about difference between NAND and NOR flip flops, and a whole lot more. Without this understanding, time is being wasted, both the OPs and list responders.

On Wed, May 28, 2025 at 07:53 PM, <guilhermesouzam01@...> wrote:

1. Can I configure which clock edge (rising or falling) my circuit will respond to? I’m assuming it is set to trigger on the falling edge in this case.

Not exactly.? This kind of flip-flop is level-sensitive, not edge-sensitive.? If I remember correctly (I might have this backwards), while the CLK is High, the state of the S and R inputs is transferred to the outputs.? On the falling edge of CLK, they become "latched in" and will remain that way until the next rising edge of CLK.

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Edge-triggered is a different arrangement, one where the outputs respond only at either the rising or falling edge (not both) of the Clock.

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FYI, you should move the edges of your signals.? Both S and R should be stable (unchanging) whenever CLK is changing state.? By having their edges coincide, it makes for very difficult analysis.? They must not do that.? Digital circuits have things called "Setup time" and "Hold time" which are requirements that should be met before and after the Clock, when the other inputs need to be stable and unchanging.

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Technically, if an S or R or D input is changing at the same moment as the Clock, those inputs are "undefined".? Could be high, could be low, could be stuck in the middle - causing circuits to go into a nasty "metastable" state, and/or just oscillate for a while.

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3. Another point is the noise on the output (Vq) right at the beginning of the simulation. Is this behavior normal?

Your simulation still has the problem that LTspice can not converge on an initial operating point.? It can't agree whether the Q output should begin High or Low.? Both are equally likely, and the flip-flop is exactly balanced so there is nothing in the circuit to direct it one way or the other.

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If you examine the SPICE Error Log, depending on which LTspice version you have, you should see messages like these:

Direct Newton iteration failed to find .op point. ?(Use ".option noopiter" to skip.)
Starting Gmin stepping
...

Gmin stepping failed

Starting source stepping with srcstepmethod=0
Could not converge to DC with sources off!
Starting source stepping with srcstepmethod=1
Could not converge to DC with sources off!
Pseudo Transient failed in finding the operating point at 20 ns.
Trouble finding operating point....skipping operating point for Transient analysis.

I underlined some of the important phrases.? What's happening is this:? LTspice tries four different algorithms in an attempt to find the initial operating point, and all four of them failed.? So it has no choice but to launch into the transient analysis without a stable operating point - which in turn leads to "funny" things happening at the start of the transient analysis.? Basically, now that the click is running, it is now able to converge, and things can progress normally.

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This is where "IC" conditions help immensely.? See eT's uploaded circuit for an example of that.

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FYI, I see nasty oscillations happening during some of the CLK cycles too.? This might depend on your LTspice version and on various settings.

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I think other things might not be right yet.

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Andy

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Hello Andy

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I've updated my circuit take into consideration all feedbacks and It's working, but I would like to check with you the points below:

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1. Can I configure which clock edge (rising or falling) my circuit will respond to? I’m assuming it is set to trigger on the falling edge in this case.

2. The first invalid state of my output happens because Vs and Vr are both at 1, and the clock is falling. Okay.
But right after that, when the clock rises to 1, my output goes to 1, even though Vs and Vr are still at 1. From my point of view, this state shouldn’t happen. Why did it change when the clock rose? Why did the output go to 1 (a stable state) if Vs and Vr are at 1 (which should produce an invalid output)?

3. Another point is the noise on the output (Vq) right at the beginning of the simulation. Is this behavior normal?

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I posted the updated circuit again in the Temp file. Its called FlipFlop_SR_Clock1.

Thanks in advance!

On Wed, May 28, 2025 at 11:21 AM, Andy I wrote:

The Ctrl-Z character, or action, was often used to mean end-of-file.? ...

This is, of course, before MS-Windows, where the Ctrl-Z keyboard action now means "Undo".? But I digress again.

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Andy

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By the way, I think the extra character is 0x1A (Hex(1A)), also known as Ctrl-Z.

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The Ctrl-Z character, or action, was often used to mean end-of-file.? A Ctrl-Z would occasionally be found within the file itself, but it was more commonly not found within a file, since the size of a file in bytes on a file system identifies where the actual end of the file is, without the need for an extra character.? But occasionally a ctrl-Z character is/was found at the end of a text file, in the file itself.

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Ctrl-Z was also used to tell the O.S. or the drivers that this is the end of a file, when typing out the contents of a file, or feeding a file through a serial link.? But I digress.? Technically, its use in ASCII was something else entirely, but in several decades I have only ever seen it used to mean end-of-file.

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In my text editors, including LTspice's text editor, it displays as a right-arrow (→) so it is not entirely non-printing.? Microsoft Word displays it as an open box, suggesting that it thinks it is non-printing.

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Andy

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On Wed, May 28, 2025 at 10:33 AM, Hawker wrote:

Turns out, on older models, TI had some non printing character (alt code?) and a spare line feed at the end of their models. LT 24.0 didn't care, but 24.1 does care.

This is a good one to report to Analog Devices.? Please do that.

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I'm not suggesting that SPICE models can or should get away with extra characters!? But if "tradition" has been that this particular non-printing character at the end of a model file was previously accepted, and if they are prevalent in large numbers of downloadable SPICE models, then I think ADI ought to restore the previous LTspice behavior and accept those models too.

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Seems all the old stuff had this, but not the newer TI models.

Yes, especially for that reason.

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BTW, the extra line feeds are not a problem.? In fact I have sometimes seen the opposite happen, where a model ends with the last line of text and no carriage-return (or line-feed), which caused a SPICE program to not read that last line.? I never saw that happen in LTspice nor PSpice, bit it did happen with HSPICE.

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Thank you this is super helpful.
This confirmed the model is good and something else was wrong.

So after googling "Expected device instantiation or directive here." I found others with the same problem and the solution.

Turns out, on older models, TI had some non printing character (alt code?) and a spare line feed at the end of their models. LT 24.0 didn't care, but 24.1 does care.
Deleting this character and the? the extra line feed from the model made this work. It also fixed other broken TI models I have.

Seems all the old stuff had this, but not the newer TI models.

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thanx for the help.