Hello Andy
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I've updated my circuit take into consideration all feedbacks and It's working, but I would like to check with you the points below:
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1. Can I configure which clock edge (rising or falling) my circuit will respond to? I¡¯m assuming it is set to trigger on the falling edge in this case.
2. The first invalid state of my output happens because Vs and Vr are both at 1, and the clock is falling. Okay.
But right after that, when the clock rises to 1, my output goes to 1, even though Vs and Vr are still at 1. From my point of view, this state shouldn¡¯t happen. Why did it change when the clock rose? Why did the output go to 1 (a stable state) if Vs and Vr are at 1 (which should produce an invalid output)?
3. Another point is the noise on the output (Vq) right at the beginning of the simulation. Is this behavior normal?
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I posted the updated circuit again in the Temp file. Its called FlipFlop_SR_Clock1.
Thanks in advance!
