Hi.
Generally speaking I don't think floating land is necessary. It is possible to calculate circuits without it.
But especially for stubborn people I have created a model of floating ground and a symbol for it. Everything is in my large collection of models.
Here are the contents of the model:
.subckt GNDFLOAT 1 Cp=1pF Rp=1G
c 1 0 {Cp} Rpar={Rp}
.ends GNDFLOAT
Make your own symbol for this model.
There can be many such floating grounds in the schematic.
Real floating grounds have this equivalent.
With galvanic isolation, there is always a small capacitance between windings. When optocouplers are used, they also have parasitic capacitance in them.
My floating ground is better than the commonly used high impedance resistors for simulation.

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On 25/05/2024 10:58, john23 wrote:

Hello, I want to simulate the effect of UCC21220AD_TRANS? floating ground in LTSPICE
My gate drive needs to create floating voltage for irf7854pbf MOSFET.
However i know that in LTSPICE floating ground is not possible.
I have attached bellow all symbols and simulation file.
How should make a floating ground in LTSPICE?
Is it possible to create two different types of ground in LTSPICE?
Thanks.

You didn't include "UCC21220AD_TRANS.LIB" in the list of required files. Neither is it in the folder you created.

And please, when you upload a schematic with models and symbols, put them all in a zip!

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I would suggest you place an appropriate resistor||capacitor pair between the real "ground" and your floating circuit's reference level net, which you can name as you wish. The resistor||capacitor combination should approximate the actual isolation characteristics you might find in the real world. It could be megohms and picofarads or gigaohms and nanofarads, but see below - those values may not even matter.

The reality is unless your floating reference net has a significantly different voltage (especially dV/dt) from LTspice's (note the spelling, LTspice - uppercase LT; lowercase spice) "ground" reference level, the isolation characteristics don't really matter much. If it does have a significantly different voltage, then modelling it might matter.

It would also be nice of you to zip those files together so that they remain associated. Somewhere, somewhen down the road, someone will want to learn from your work and all these separate files make finding the right bits to use more difficult for them.

Donald.

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On 25/05/2024 10:17, Tony Casey wrote:

On 25/05/2024 06:22, john23 wrote:

Hello, I have in my lab an evaluation board for CGHV1A250F.
It will be incorporated to the CGHV1A250F chip into a bigger design.

Currently because its a Vds=45 and Ids=15 when rf is runnning then i see it as 3Ohm resistor.
but the problem is that i need to pick a suitable gate driver so the capacitance on the gate will charge .

how can i do? basic " spice model" so i could put into a simulation?

Thanks.

I presume you're planning to use the CGHV1A250F for its intended purpose as a high power RF amplifier for the 8.8-9.6GHz range. To think of it as switching transistor, whose gate has to be driven from a "gate driver" is entirely wrong. Viewing it as a "3Ohm resistor" is completely misguided. If this isn't your application, then you need to consider carefully what you need to do, as this almost certainly isn't the right device.

As far as I can see, the CGHV1A250F is internally matched for use in a 50Ω system. If you want to use it in an LTspice simulation, you need to download its from the new supplier (MACOM), convert those to a generic SPICE model with the S2SPICE program. You can use the S2PORT port symbol that can be found in the group's file archive, link that to the converted SPICE model, and construct a simple .AC analysis with a 50Ω source and 50Ω load. You won't be able to do a sensible non-linear analysis (.TRAN) because there is no data available for this device. There isn't even a datasheet available from the current supplier, unless you specially request it, presumably signing an NDA (non disclosure agreement) as well, although the old Wolfspeed one is downloadable from the URL you included. I'm surprised you managed to get an Eval Board. Digikey stock the devices at the one-off price of $789!

Frankly, LTspice isn't the right tool to be using for design in this frequency range.

I have uploaded a Test Schematic.

--

Hello, I want to simulate the effect of UCC21220AD_TRANS? floating ground in LTSPICE
My gate drive needs to create floating voltage for irf7854pbf MOSFET.
However i know that in LTSPICE floating ground is not possible.
I have attached bellow all symbols and simulation file.
How should make a floating ground in LTSPICE?
Is it possible to create two different types of ground in LTSPICE?
Thanks.


/g/LTspice/files/Temp/john23/UCC21220AD_TRANS.asy
/g/LTspice/files/Temp/john23/irf7854pbf_test.asy
/g/LTspice/files/Temp/john23/UCC5304_Simplis_Test5.asc

/g/LTspice/photo/294510/3786158?p=Created%2C%2C%2C20%2C2%2C0%2C0

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On 25/05/2024 06:22, john23 wrote:

Hello, I have in my lab an evaluation board for CGHV1A250F.
It will be incorporated to the CGHV1A250F chip into a bigger design.

Currently because its a Vds=45 and Ids=15 when rf is runnning then i see it as 3Ohm resistor.
but the problem is that i need to pick a suitable gate driver so the capacitance on the gate will charge .

how can i do? basic " spice model" so i could put into a simulation?

Thanks.

I presume you're planning to use the CGHV1A250F for its intended purpose as a high power RF amplifier for the 8.8-9.6GHz range. To think of it as switching transistor, whose gate has to be driven from a "gate driver" is entirely wrong. Viewing it as a "3Ohm resistor" is completely misguided. If this isn't your application, then you need to consider carefully what you need to do, as this almost certainly isn't the right device.

As far as I can see, the CGHV1A250F is internally matched for use in a 50Ω system. If you want to use it in an LTspice simulation, you need to download its from the new supplier (MACOM), convert those to a generic SPICE model with the S2SPICE program. You can use the S2PORT port symbol that can be found in the group's file archive, link that to the converted SPICE model, and construct a simple .AC analysis with a 50Ω source and 50Ω load. You won't be able to do a sensible non-linear analysis (.TRAN) because there is no data available for this device. There isn't even a datasheet available from the current supplier, unless you specially request it, presumably signing an NDA (non disclosure agreement) as well, although the old Wolfspeed one is downloadable from the URL you included. I'm surprised you managed to get an Eval Board. Digikey stock the devices at the one-off price of $789!

Frankly, LTspice isn't the right tool to be using for design in this frequency range.

--
Regards,
Tony

Hello, I have in my lab an evaluation board for CGHV1A250F.
It will be incorporated to the CGHV1A250F chip into a bigger design.

Currently because its a Vds=45 and Ids=15 when rf is runnning then i see it as 3Ohm resistor.
but the problem is that i need to pick a suitable gate driver so the capacitance on the gate will charge .

how can i do? basic " spice model" so i could put into a simulation?

Thanks.

https://pdf1.alldatasheetde.com/datasheet-pdf/download/1673867/WOLFSPEED/CGHV1A250F.html

Could someone tell me how can I write the charge equation provided in both the papers if I want to model a nonlinear capacitor? I have written a single equation before but here we have three equations for three conditions. How to write these equations including the conditions?

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On 24/05/2024 11:37, ericsson.sunshine via groups.io wrote:

Thank you for the opinions replied.

I found another method, to record all recursive paths into single line for every recursion path in old LTspice V.17.
It's using the 'dos command window' app, then go to the lib directory maybe 'C:\Users\account\Documents\LTspiceXVII\lib',?
type 'dir /A:D /B /S > all_dir_path.txt', all recursion paths will be saved in the file 'all_dir_path.txt', in an ideal world , it should be solved once.
But it seems new problem happened, it's

1. The content that can be saved in the text box of 'Tools -> settings -> Search Paths -> Symbol Search Path/Libray Search Path' seems having word length bytes limits.
2. If the symbols or libs have the same name in different recursion paths , it can tell which is the original path of the .asc file saved in LTspice V.17 when run it in new LTspice V.24. I guess it's because the ranking order lists in the search paths in LTspice V.24. But I don't quite know the searching rule of this recursive feature in LTspice V.17. -> Such that , have no idea how to rank those path lists.

Thank you for the sharing.

Personally, I don't find the Sym path feature useful at all, because it is non-recursive. Arguably, there is no reason why the Lib path needs to be recursive. The standard lib\sub folder has all the models in it, so the user's lib folder can have every model the user has added, with the only drawback that the user needs to manually maintain it. So, I use the Lib path feature.

I've mentioned it before, but my solution to selection of user's symbols is:

1. Keep the user's symbol folder structure similar to the default one
2. Make a symbolic link from the top level user's folder into the top level default folder

Then the user's symbol library appears in the symbol chooser (F2) under whatever name you give to the symbolic link - I call it "Supplementary". Unlike the standard component libraries, the V24 Component Update process doesn't remove the added symbolic link each time each time it's run. But just in case that changes in the future, it would only delete the symbolic link, not the actual user's symbol folder, and can easily be restored.

The problem still remains that when you use your own symbols from your own library, you must remember to manually search them out and add them to any zip of a shared schematic. I guess I probably manage to do that about 90% of the time. An "archive" feature would be a solution to this issue, but one doesn't exist yet.

--
Regards,
Tony

Hi, :

Thank you for the opinions replied.

I found another method, to record all recursive paths into single line for every recursion path in old LTspice V.17.
It's using the 'dos command window' app, then go to the lib directory maybe 'C:\Users\account\Documents\LTspiceXVII\lib',?
type 'dir /A:D /B /S > all_dir_path.txt', all recursion paths will be saved in the file 'all_dir_path.txt', in an ideal world , it should be solved once.
But it seems new problem happened, it's

1. The content that can be saved in the text box of 'Tools -> settings -> Search Paths -> Symbol Search Path/Libray Search Path' seems having word length bytes limits.
2. If the symbols or libs have the same name in different recursion paths , it can tell which is the original path of the .asc file saved in LTspice V.17 when run it in new LTspice V.24. I guess it's because the ranking order lists in the search paths in LTspice V.24. But I don't quite know the searching rule of this recursive feature in LTspice V.17. -> Such that , have no idea how to rank those path lists.

Thank you for the sharing.

Best regards.

abid asked, "what's the difference between?hierarchical sub-schematic and subcircuit? Are they the same?"

Yes and no.? Mostly no.

A schematic is a diagram that you can draw.

A subcircuit is a block of SPICE netlist lines.

A hierarchical sub-schematic ends up creating a subcircuit, when the whole schematic is turned into a SPICE netlist.? Until that moment, it is not a subcircuit yet.? After being turned into a subcircuit, LTspice then expands the netlist and effectively eliminates all the subcircuits, so it is a temporary state of the netlists.

"In the schematic that Tony uploaded, is it necessary to write the following lines? Won't just using the symbol work?"

Yes to the first, and no to the second.? A symbol is JUST AN ICON, or a PLACE-HOLDER.? It has no function of its own.? The subcircuit text is necessary because it has the circuit that the symbol represents.? The symbol means, "I want that subcircuit to be used here."? But the subcircuit needs to be defined, by having it there on the schematic.? All of the lines, from .SUBCKT to .ENDS, must be somewhere, either on the schematic itself, or in a separate file.? It is not in the symbol.

Andy

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On 23/05/2024 20:47, abid wrote:

Thanks. I had some questions. How do I create the SRD subcircuit?

*
.subckt SMMD805 1 2
Lser 1 11 1n
Cpar 11 2 2p
D1 11 2 D_805
*

What does Lser, Cpar, D1 mean? Also what does the numbers beside these parameters mean?

.MODEL D_805

Should it be .MODEL SMMD805?

?

How do you create the SRD symbol? And then use it in a pulse generator? I would really appreciate if you could explain these things a bit.

Thanks all for all the help. I guess my question is how do I create an SRD from scratch and how do I make it a subcircuit for bigger circuits.

?

Also, in both the IEEE paper and the researchgate paper attached earlier, there is a charge equation. Can I incorporate that equation while creating SRD??

Lser and Cpar are the the internal bond wire and package capacitance, respectively. They are actually present in all packaged semiconductor devices but cannot be incorporated into .MODELs and are usually not considered. Since they become more important at high frequencies, they are usually added for high frequency devices. The naming of this .MODEL is purely arbitrary, since it not exposed to the outside world. I suspect it is abbreviated to D_805 because this die is incorporated into other physical diodes in different packages, which are embedded in different .SUBCKTs with different Lser and Cpar values to suit the different packages.

The charge equation is largely satisfied by appropriate choice of parameters in the diode .MODEL - in particular CJ0, VJ, M, TT - which is embedded in the .SUBCKT.? (BTW, LTspice is not case-sensitive, I use CAPS purely for emphasis.)

You will find answers to your other questions when you have used LTspice for longer. You cannot become an expert in a day, or even a month.

--
Regards,
Tony

what's the difference between?hierarchical sub-schematic and subcircuit? Are they the same?

?

In the schematic that Tony uploaded, is it necessary to write the following lines? Won't just using the symbol work?

.subckt SMMD805 1 2
Lser 1 11 1n
Cpar 11 2 2p
D1 11 2 D_805
*
.MODEL D_805 D(IS=500.0E-15 N=1.3 RS=0.13
+ CJ0=4.55E-12 VJ=0.5 M=0.235 XTI=3.0
+ EG=1.12 BV=60 IBV=10E-6 TT=30E-9)
.ends SMMD805
*

Also, if Tony is seeing this, could you please upload the schematic from which you created the SRD symbol? Thanks.

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It's most likely a typo. "C" and "D" are adjacent on a UK keyboard. Having not noticed initially, it proliferated and I have loads of files prefixed with "SRC" in that work folder. ?

--

abid,

In many SPICE programs (which might include LTspice), the built-in diode model's diode capacitance follows these formulas:

C = Cj*area + Ct

Cj = Cjo*(1-Vd/Vj)^-M for Vd ≤ Fc*Vj
? ? = Cjo*((1-Fc)^(-M-I))*(1-Fc*(1+M)+M*Vd/Vj) for Vd > Fc*Vj

Ct = TT*area*(d(Inrm*Kinj+Irec*Kgen)/dVd)

But some of the parameters above also are functions of temperature.? It gets complicated.

Andy

abid,

The circuit that is shown in 4.png represents a circuit of a diode and the package parasitics, and maybe a bit more.

The basic diode (and transistor) models in SPICE are good for on-chip semiconductors but incomplete for separately packaged components which typically have lead inductance and capacitance of the attachments.? When someone needs the added detail of package parasitics, they can add them separately.? In 4.png, that includes Cp, Ls, and probably Rs.? Capacitor Cj might be part of that too, but Cj(V) depends on voltage so it is more than just that.? The built-in diode model in SPICE already has a junction capacitance Cj(V) that depends on voltage, so adding another one is normally not needed.? On the other hand, if the SPICE diode's Cj(V) can not be adjusted to fit the actual diode's Cj(V) with enough accuracy, then they might add the separate capacitor shown in 4.png.

It is difficult to answer your questions about Cj(V).? As I say, SPICE's built-in diode model already has a Cj(V) that depends on voltage in the way that most diodes do.? But sometimes people want to "take control" and do it their own way, instead of using the built-in SPICE models.? I do not know if step-recovery diodes have different capacitance Cj(V) than "other" diodes.? Since SRDs are used in extremely high frequency circuits, it's probably important to get that characteristic just right.

This probably does not entirely answer your question, especially how it relates to equation 2 in one of the papers.

Andy

Thanks Andy for the clarification. I think I have started to get things. I am confused about the circuit model of the SRD. Different papers have used different circuits. I have uploaded a circuit model here (4.png) /g/LTspice/album?id=295221. For this one, do I need to model the Cj(V) too in the subcircuit? In that case, can I use the equation (2.png) to model the Cj(V)? What I am trying to know is what is the LTspice equivalent of figure 1(a) of the picture (1.png)

?

If Tony or someone could upload the schematic from which the subcircuit's (SRD) symbol is created, that would be great for me to understand. Thanks.

abid wrote, "What does Lser, Cpar, D1 mean?"

Those are SPICE Netlist elements.? Any element beginning with an 'L' is an inductor.? 'C' is for capacitor.? 'D' is for diode.? The names Lser, Cpar, and D1 were arbitrarily chosen.

There are many, many references about SPICE where the simple stuff like that is described.? LTspice's Help talks about it too.

"Should it be .MODEL SMMD805?"

No, it should be '.MODEL D_805 D ....? That line (actually it's 3 lines with the continuation characters) defines a diode named "D_805", which is the one used in the Netlist line "D1 11 2 D_805".? That element is PART OF the subcircuit named "SMMD805".? The subcircuit includes a series inductance (Lser) and a parallel capacitance (Cpar).? The basic intrinsic SPICE diode has no package parasitics such as inductance, so a common thing to do is to enclose an intrinsic diode inside a subcircuit with those extra elements.? That is what the figures show, in the papers you referred to.

"How do you create the SRD symbol? And then use it in a pulse generator?"

He drew it.? LTspice has a symbol editor too.

It is used in the pulse generator by having that symbol as part of the pulse generator's schematic.

Symbols don't actually "do" anything.? The symbol for a resistor is a rectangle or a squiggly line, but the symbol is not the model, and does not affect the V/I relationship.? The symbol is just an icon.

None of these questions really help with the problem of creating a SRD model from scratch.? The electrical details of the SRD are a (potentially) complicated subject, which I have not even attempted to describe here.? If you plan to simulate things in LTspice, you should take the time to learn LTspice, and then learn how to model an SRD.? They are two completely separate things.

Andy

On Thu, May 23, 2024 at 03:18 AM, Tony Casey wrote:

I have uploaded one of my old schematics that uses the SRD in shunt mode, which is often more useful than the series mode.

Thanks. I had some questions. How do I create the SRD subcircuit?

*
.subckt SMMD805 1 2
Lser 1 11 1n
Cpar 11 2 2p
D1 11 2 D_805
*

What does Lser, Cpar, D1 mean? Also what does the numbers beside these parameters mean?

.MODEL D_805

Should it be .MODEL SMMD805?

?

How do you create the SRD symbol? And then use it in a pulse generator? I would really appreciate if you could explain these things a bit.

Thanks all for all the help. I guess my question is how do I create an SRD from scratch and how do I make it a subcircuit for bigger circuits.

?

Also, in both the IEEE paper and the researchgate paper attached earlier, there is a charge equation. Can I incorporate that equation while creating SRD??

?