On Fri, May 31, 2024 at 03:53 AM, Tony Casey wrote:

Hi, thanks for the responses. By real model I mean not the one that came with LTspice "dflop" or a model with parameters
of a real component. In other words "Real ~ More accurate".

I came across this site for sharing LTSpice models: ?

It seems pretty dated but has a model I'd like to look at,? but I wasn't able to get the registration process to complete.???? Just wonder if anyone knows the status or has the ability to download a model for me?
Thanks and 73,
Bob W9RAN

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On 31/05/2024 10:24, eewiz via groups.io wrote:

took a copy of an original project and did; "C:\Win32\LTC\LTspice24\LTspice.exe -netlist Original.asc" in a dos window.
I renamed the net listing to BatchOriginal.net so it does not get clobbered by running "Original.asc" again.

I made sure that all .spice directives had been removed from the copy of the original before net listing it.

I then created a new "Batch.asc" schematic and placed all .param .tran etc... onto the new "Batch.asc" schematic.

I then added ".inc BatchOriginal.net" to the "Batch.asc" schematic.

Then I planned to create many appropriately named copies of the "Batch.asc" schematic to do a multitude of batch runs on the "BatchOriginal.net" project all with differing .params to get a multitude of "Original.mout" files to go to Excel for analysis.

?

Now for the issue.

I have uploaded a working example that detailes the issue.

Any subcircuit device that has pin numbers creates usable measurements.

Any subcircuit device that has pin letters fails to creates usable measurements.

?

Run the "Original.asc" file and all is well. All six measurements work correctly.

Next, run the "Batch.asc" file which .includes the BatchOriginal.net file. Only the first three measurements work correctly.

There is no need to run it in batch mode. Using the GUI will prove the point.

The last three measurements fail. In the plot window as well as in the measurements found in the log, "Ctrl-L".

The working measurements are all of components with pin numbers.

The failing measurements are all of components with pin letters.

The reason your measurements don't work and the bottom 3 traces aren't shown is that those exact named traces don't exist in the batch version. See /g/LTspice/photo/295376/3787948?p=Name%2C%2C%2C20%2C1%2C0%2C0.

Some of the traces have been renamed: those that involve current into subckt pins. You could restore your traces and .MEASurements by renaming the expressions being plotted to match those that are available. You can press Ctrl-A from the waveform viewer to added those (re-named) traces to the blank panes. Obviously, the expressions in the .MEAS directives need to be changed too.

Why this happens is another matter. All of the currents that involve U4 and U5 have had their pin names silently changed. The symbols for U4 and U5 have got only alphabetic pin names. Those have all been changed to be numeric. I presume the pin orders have been maintained. What's puzzling is the U1 has also got one purely alphabetic pin name: U1:K - this hasn't been been renamed and Ix(U1:K) exists in the list of available traces from the batch mode simulation.

Obviously, a possible workaround for this that avoids having to edit the trace names is to change the symbols that you're using to use only numeric pin names. Tut that's not a proper solution.

What I think is happening, is the the issue occurs where pin names in the models doesn't match those used in the symbol. When a simulation is run using the netlist in batch mode, the traces names assigned on the basis of the .subckt pin names, because the batch process has no knowledge of the symbols because they are irrelevant. When the simulation is run from the schematic, LTspice uses the symbol pin names when building trace list. In the case of the BAV70 (U1), the model names match the symbol names, so problem occurs. For the TL431, the pin names don't match, so the trace names don't match either.

I think that's it. In the cases where the pin names don't match, either the symbol or the model should be edited to fix that.

--
Regards,
Tony

eewiz,

I suspect that some of your original SPICE models have changed, since the time you first ran those simulations.

e.g., your TL431.mod now has only numeric pin numbers internally.? But your "Original.meas" file tries to refer to non-numeric pin names which TL431.mod no longer has.? I believe your TL431.mod changed over time, and your other (.plt and .meas) files do not reflect the changes.

Andy

abid wrote, "Do you have any idea how should I connect the DC bias?"

I forgot to answer that part of the question.

Your schematic in 5.png shows that the DC voltage source is applied (connected) to the circuit at the junction between R2 and C2 on that schematic.

Therefore, the right end of your R1 should go to the DC voltage source, and the other end of that voltage source is grounded.? Then, your C1 would be in parallel to the voltage source, between the right end of your R1 and ground.? But in the simulation, voltage sources are ideal, therefore bypassing an ideal voltage source with a capacitor does nothing useful.? So your C1 would not be necessary for the simulation (if the voltage source is ideal as they usually are).? But the real circuit should have it, because real voltage sources are never ideal.

I agree with Tony that you need to understand what is going on, especially before jumping headlong into a microwave project like this.? Designing at these frequencies is challenging even for experienced engineers who have been working with circuits for years, maybe even decades.? It sounds like you have not been doing that for as many years.? It can be fun to experiment, especially on paper or in a simulator, but you can't expect anything to work without actually understanding the circuits, to such a level that you can answer most of your own questions.? I think a lot more research and study about these circuits is needed before progress is possible.

Andy

I just want to mention this:

I believe your use of the word "Batch" is different from LTspice's "Batch".? The word "Batch" has special meaning in LTspice, where it refers to running simulations that do not require human intervention because they run in the background.? I suspect you did not mean that (but maybe you did?).

LTspice's "batch" mode is activated by adding "-b" to the command-line.? Also with the "-FastAccess", "-netlist", or "-PCBnetlist" command-line switches.

LTspice's "batch" comes from MS-DOS's "batch" where programs can be run and controlled from a .BAT (batch) file.

Andy

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On 31/05/2024 01:31, abid wrote:

I think so too but I can't figure out what's wrong. How do I draw the V1 along with the L1,R1 and C1 so that it is like the top part of 5.png? I am really frustrated and I have to come up with the result by tonight. Really appreciate the help.

Look, you can't hope to "design" a circuit like this by copying an unlabelled schematic and guessing what the values of the circuit might be. In any event, you have copied it wrong. In the photo, the DC source and C2 are in parallel. You have drawn them in series on your schematic. Do you know what the purpose of V1 is?

Start with the basic requirements of the circuit:

1. Is the operating frequency really 1MHz?
2. Do you need to operate over a range of frequencies?
   
3. What final pulse width (FWHM) are you trying to achieve?
4. What pulse amplitude do you want?

You can't make a start on the design until you know the answers to these questions. For example, the choice of diode is governed by the answers to all of these questions. SRDs are available in a range capacitances and breakdown voltages. Each diode's datasheet will also include the minority carrier lifetime and the transition time. All the parameters are interdependent.

I previously uploaded a working circuit. It might not do exactly what you want, but it formed the basis of something that was developed and used in production. Did you study how it worked? All the values in that circuit were chosen carefully considering the requirement. I notice you used the SRD model that I provided in that schematic, but went and changed it by adding random stuff that wasn't needed.

Forget about the NLTL stuff until you have got a basic SRD pulse generator working. The design of NLTLs is quite tricky and certainly can't be done by throwing random inductors and varactor diodes at the schematic. It might not even be appropriate for your purpose.

Have you plotted just the V and I characteristics of an SRD to demonstrate the exaggerated delayed "snap" recovery from forward conduction? This is what you need to understand about the process to effectively design the circuit. Start simple, and then progress when you understand what's happening and why. Here is the definitive summary of the SRD operation and design of pulse generators using them: .

--
Regards
Tony

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On 31/05/2024 01:17, gioffantasy@... wrote:

Hi everyone, is there any model for a Type D Flip Flop? I've been working with the dflop from LTspice library modifying his parameters,
but now I would like to do some tests with a real model. I need a model FlipFlop with a propagation delay around 4ns, and frequency over 100 MHz.

I couldn't find any LTspice model on some of manufacture's page like TI or ONSEMI, just IBIS files.

I guess you didn't find on the TI website?

There are also a number of models for various types of '74 flip-flop in the group's file archives, e.g.: /g/LTspice/filessearch?p=name%2C%2C74%20flip-flop%2C20%2C1%2C0%2C0&q=74%20flip%20flop

What do you mean by "real model"? By definition, all models are not "real". Some models are just more accurate than others.

--
Regards,
Tony

Thank you so much for this, Andy!

?

Do you have any idea how should I connect the DC bias? Clearly my way is wrong. Would appreciate the help. Thanks.

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Jerry Lee Marcel wrote, "That's why I asked the OP what issue he has, because his .asc runs good with me."

I think you are in the minority.? Did you have the Alternate Solver enabled??

Yes.

re: "U2's non-inverting input is perfectly referenced to ground ..."

And that is part of the problem.? Nothing else in the circuit is referenced to ground.? The rest of the circuit does not know what or where Ground is.? It is a foreign node with an unknown voltage seen by the rest of the circuit.

I don't see it like that. There is galvanic continuity for every node in the circuit.

re: "Of course, the circuit has 0dB gain because the Vref node is a high-Z one."

Neither of those is right.

The circuit has significant voltage gain from IN to OUT0.

That's not what I see.

The Vref node is in a feedback loop so it is low-Z, not high-Z.? U1 drives Vref to the same voltage as the junction of R1 & R2.

The junction of R1 & R2 is floating. If you probe Vp or Vn, you can see that a sinewave of amplitude equal to the input signal is superimposed, so, to me, it looks like a very high impedance for the NFB loop return.

However, what's happening is that the sine wave voltage source V2 drives the ENTIRE circuit up and down by a sine wave.? Every node in the circuit, except for the Ground node, has (almost exactly) the same 10 kHz, 10 mV sine wave signal on it.?

That is correct.

That's not the same thing as having no gain; it's a positive gain acting on no signal.?

I won't argue about semantics.To me, it acts upon the NFB loop.

abid wrote, "I thought srd1.asy is the symbol for the subcircuit srd1.asc and I am using the symbol in the main schematic. Could you please explain why it's schematic hierarchy?"

Open the symbol srd1.asy in LTspice.? Press Ctrl-A (or go to Edit > Attributes > Edit Attributes).? At the top of the pop-up window, note the selection for Symbol Type.

• Cell -- to use the symbol with a .SUBCKT ... .ENDS block of text (and ignore srd1.asc)
• Block -- to use the schematic srd1.asc (which might or might not ignore the .SUBCKT ... .ENDS block of text)

Symbol Type = Block is an example of schematic hierarchy.? Your main schematic (SRD_NLTL.asc) is the top-level in that hierarchy, and your other schematic (srd1.asc) is a lower-level schematic in that hierarchy, which gets called by the symbols on the main schematic.

If you use Symbol Type = Block, the symbol's name must match the schematic's name that it will call - except for their filename extensions, of course.? And that filename must have no spaces.? Also, all the symbol's Attribute lines should be blank.? Also, the Pin Names in the Symbol must match exactly their net names on the schematic.? On the schematic, they were named "1" and "2", but in the symbol, they were named "+" and "-", so that needs to be fixed.

With the symbol srd1.asy open in LTspice:

1. Press Ctrl-A to open the Attribute Editor.
2. Change Symbol Type from "Cell" to "Block".
3. Delete the "X" on the Prefix line.
4. (The Description line probably can be left as it is.)
5. Click "OK".
6. Right-click on the upper pin and change its Label from "+" to "1" to agree with the schematic, and click OK.
7. Right-click on the lower pin and change its Label from "-" to "2" to agree with the schematic, and click OK.
8. Click the Save toolbar button, or go to File > Save.

It's best to close and re-open the main schematic, so that changes are re-loaded.

On the schematic, delete (or turn into a Comment) the block of text that defined the SRD1 subcircuit.

re: "And if the symbol type is Block, then in the main schematic, what will be the Instance name and PARAMS if I click the symbol?"

The Instance Name is unimportant, but you can change it if you don't like the name LTspice used.? Instance names are just labels on the schematic.? They are labels such as "R5" or "D1".

Use the PARAMs only when you wish to pass parameter values (changeable numbers) to the lower-level schematic.? In your case, there is one lower-level schematic srd1.asc, but it is in three places on the main schematic.? Each one of the three could pass different parameter values, for the same lower-level schematic.? You might do that if the three instances represented diodes or capacitors with different values.? Otherwise, ignore it.

Now that it is set up to use the schematic srd1.asc, changes to srd1.asc affect the main simulation.? Those changes can include the diode's .MODEL statement, or capacitor or inductor values, even the structure.? You can add or delete components in the schematic srd1.asc and re-run the simulation, without editing any .SUBCKT .... .ENDS block.

Notice that LTspice already has a MV2201 diode model.? Here is your model compared to LTspice's:

.model MV2201 D(Cjo = 4.3p,Bv=60,M = 0.235,Vj=0.5)
.model MV2201 D(Is=1.365p Rs=1 Cjo=14.93p M=.4261 Vj=.75 Isr=16.02p Nr=2 Bv=25 Ibv=10u Vpk=25 mfg=OnSemi type=varactor)

Some of the parameters are very different.? I think LTspice uses its own model instead of yours (because it is defined after the other).? If you want to use yours, rename it everywhere.

Andy

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Hi Andy,

Tom,

I understand what you're saying, and yes there is pretty good experience simulating them in the way you described, by changing the Vn node to GND.? It fits what I wrote earlier that it should not make much difference which net you choose to call Ground, other than changing how you go about plotting and measuring voltages.? (But sometimes it matters because of the manufacturer's models.)

But it also got me thinking, is there any reason not to ground the Vref node?? Is grounding the Vn node actually better?? I'm not trying to detract from grounding the Vn node.

Grounding the Vn node seems to "feel" better than grounding a node that is being driven by an op-amp's output; but is it really better or does it just "feel" that way?

AC-coupling the input signal would be unnecessary (for the simulation) if it is a voltage source that is referenced to the supply's midpoint, or Vref in this circuit.

Andy

On Thu, May 30, 2024 at 04:13 PM, Andy I wrote:

I think there are two main sections of the circuit.? The first is the initial pulse generator, using the step recovery diodes (and V2, C2, L2, L1, R1, R2, and R3), and maybe V1.? But the way you drew it, V1 does nothing, which means L1 and R1 do nothing too.? Did you intend to draw it that way?? I think you made a mistake.

I think so too but I can't figure out what's wrong. How do I draw the V1 along with the L1,R1 and C1 so that it is like the top part of 5.png? I am really frustrated and I have to come up with the result by tonight. Really appreciate the help.

gioffantasy asked if there is "any model for a Type D Flip Flop".? LTspice has the "dflop", built-in.? Is that the one you are using?

If you need a SPICE model for an actual real D-flop, choose a part number first, then search for that part number in the group's files.? If my memory is right, there are several in our group's Files.? Searching for "74LS74" or just "LS74" reveals many.

Note that LTspice is SPICE, and PSpice is SPICE, and most (not all, but most) PSpice models work just fine in LTspice too.? But there are some exceptions.? Don't bother searching for "LTspice models" on manufacturer's websites because very few call them that.? But if they call it a "SPICE" model or a "SPICE2" model or a "SPICE3" model, it is almost a guarantee that it works in LTspice.? Even if they call it a "PSpice" model, it probably works.

Andy