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Re: Photodiode

 

Hello,

A photo diode is simply a large area diode. The large area results in large capacitance Cjo. The incident light will be converted to current in the photo diode. Thus the second part of the model is simply a current source with current proportional to the amount of received light. This current source is parallel to this diode.

The file "all_files.htm" with links to every file is here:


Search in all_files.htm with "photo" and open/run the examples you will find.

The do a second search with "solar".

Best regards,
Helmut
Re: Analog Switch model with charge injection?

 

Hello,

The most simple solution will be one or two capacitors. One between the control voltage and the switch-input and the other between the control voltage and the switch-output. You can add some voltage dependence if you use a diode(Cjo) in reverse operation instead of a fixed capacitance.

Best regards,
Helmut
Re: Current Step Algorithm

ehydra
 

Hi JH -

Sorry, I can't help you because it looks to complicated what you have done.
Maybe it helps if you post the whole circuit. Even then the result thru help is not a whole faster reconfiguration but with new parameter settings. tripdt etc.

It is maybe faster to not use compares but formulate all as
float-operations: mul, div.

max/min is not in the help-file because the whole counter circuit is a hack and surely not very liked by Mike.

- H.


tindelsurf@... [LTspice] schrieb:

Henry,
I was able to figure it out with your help... and got my simulation
time down to ~4.25 minutes, a great improvement... but now I at least
know that the count table isn't what is slowing me down
significantly. I just have a complex loop. And as Helmut pointed
out... I knew the DFF solution wasn't very stable.
One final question: is there a good way to speed up the transitions
of the Sample and Holds? I tried using td/trise/tfall, but it didn't
appear to effect anything.
Thanks for giving me the hint on the max/min counts too... that
helped a lot! I couldn't find anything in the help files about that!
Love this place - you guys always get me pointed the right direction.
Just FYI - if anyone ever reads this again (the yahoo search sucks,
so I doubt it)... I was able to make Henry's suggestion a window
comparator by setting Vdir to be centered about 0 and making the
following statement for B1:
V=if(V(dir)<-0.05,-1,if(V(dir)>0.05,1,0)). I also speed up the clock
to 1k to get my 1ms count increments.
Analog Switch model with charge injection?

[email protected]
 

I am looking for a model of, for example, a DG201 analog switch, that models the actual MOSFETS used in the switch. ?I would like the simulation to show the charge injection that takes place during switching. ?Any other analog switch of this generation would be fine, too. ?I know that Analog Devices has models that use "switch" elements, but I am looking for something that is a little more real. ?Does anyone know about these parts? Would someone know ?of a MOSFET model that is good for this generation??

Thanks in advance

?
Re: Current Step Algorithm

 

Henry,

I was able to figure it out with your help... and got my simulation time down to ~4.25 minutes, a great improvement... but now I at least know that the count table isn't what is slowing me down significantly.? I just have a complex loop.? And as Helmut pointed out... I knew the DFF solution wasn't very stable.

One final question: is there a good way to speed up the transitions of the Sample and Holds?? I tried using td/trise/tfall, but it didn't appear to effect anything.

Thanks for giving me the hint on the max/min counts too... that helped a lot!? I couldn't find anything in the help files about that!

Love this place - you guys always get me pointed the right direction.

Just FYI - if anyone ever reads this again (the yahoo search sucks, so I doubt it)... I was able to make Henry's suggestion a window comparator by setting Vdir to be centered about 0 and making the following statement for B1: V=if(V(dir)<-0.05,-1,if(V(dir)>0.05,1,0)).? I also speed up the clock to 1k to get my 1ms count increments.


JH
Re: Photodiode

 

Emre wrote:

? ?"so i need photodiode model. But i couldn't found any photodiode spice model."

You could have looked for photodiode SPICE models in this group's Files area. ?There are several there already.

Go to the [LTspice] group's main webpage and read the instructions there about downloading and searching the "Table of Contents" list. ?Then search it for "photo" and see what comes up. ?(Don't search only for "photodiode" because that won't find "photo diode" or "photo-diode" etc.) ?When you find a link in that listing, click on it and your web browser will take you to the directory where the file can then be downloaded.

And as Dan says, go directly to the manufacturer's website and look for SPICE models.

Regards,
Andy
Re: Photodiode

 

If you are trying to simulate the behaviour of a photo diode used as a radiation detector - Good Luck!

You can find PSpice models for a number of photodiodes at Vishays home page.

But!

You can't just state - a photo diode! There are different underlying technologies that are exposed to light. All with a different behaviour.

Grab one of the models in Vishays zip archive amd modify to your diode spec.

Cheers

Dan Andersson, M0DFI


On 20 May 2014 06:06:06 -0700
"emreozupek@... [LTspice]" <LTspice@...> wrote:

Hello everyone,
I am working about Photo current curcuit
so i need photodiode model. But i couldn't found any photodiode spice model.
I'll glad for help
(i am using bpv10nf-vishay)


Emre OZUPEK
Electrical and Electronics Engineer
Photodiode

[email protected]
 

Hello everyone,

I am working about Photo current curcuit
so i need photodiode model. But i couldn't found any photodiode spice model.
I'll glad for help

(i am using bpv10nf-vishay)

Emre OZUPEK

Electrical and Electronics Engineer

?
Re: incrementable voltage counter

ehydra
 

I think a positive real td is implicit here because if not the CLK input can't be a clock. One of it's phase would be removed and the signal would be static thereafter.

Or?

- H.


Vlad imbvlad@... [LTspice] schrieb:

I forgot to say it: you should add one of
td/trise/tfall/tau/[Rout,Cout] (as Helmut reminded recently) to at
least one of the A devices and the inverter. As it is now, it works
but, because of the loop, it may cause problems in larger circuits.
This is similar to the DFLOP problem: if td=0 then _Q and D will have
the same states, but _Q needs to change because of D, hence the "time
step too small" errors.
Re: incrementable voltage counter

ehydra
 

Thanks Vlad! I'm proud of it.

One can add limits on both extremes. I upload an example. So add a programmable divider, phasedetector and a VCO and you have a digital PLL.

It shows all possible states.

Another fine idea is to 'substract' two of it (add a b-source which minus the outputs) for having a add/subb counter with two separate CLK inputs.

Don't forget it won't work if the float-variable mantissa overflows! 23bits good for 8 millions hits.

About your suggestions I have to think. Thanks.

- H.


Vlad imbvlad@... [LTspice] schrieb:

Look for counter_3.zip !
Nice job! If you want to avoid the behavioural voltage (not necessarily,
but recommended), you could replace it with an E or a G source with
"table(500m,-1,501m,1)" and then you're as fast as it gets. My choice would
be a G source with A2's output as resistance (which will have to be
specified to Rout=1, it defaults to 1k).
Re: incrementable voltage counter

 

I forgot to say it: you should add one of
td/trise/tfall/tau/[Rout,Cout] (as Helmut reminded recently) to at
least one of the A devices and the inverter. As it is now, it works
but, because of the loop, it may cause problems in larger circuits.
This is similar to the DFLOP problem: if td=0 then _Q and D will have
the same states, but _Q needs to change because of D, hence the "time
step too small" errors.

Vlad
______________________
ltspicegoodies.ltwiki.org -- holding, among others:
a universal analog/digital filter, block-level models
for power electronics (and not only), math blocks
with a more stream-lined approach, some digital
ADC, DAC, (synchronous-)counter, JKflop, etc.
Re: incrementable voltage counter

 

> Look for counter_3.zip !

Nice job! If you want to avoid the behavioural voltage (not necessarily, but recommended), you could replace it with an E or a G source with "table(500m,-1,501m,1)" and then you're as fast as it gets. My choice would be a G source with A2's output as resistance (which will have to be specified to Rout=1, it defaults to 1k).


Vlad
______________________
-- holding, among others:
a universal analog/digital filter, block-level models
for power electronics (and not only), math blocks
with a more stream-lined approach, some digital
ADC, DAC, (synchronous-)counter, JKflop, etc.
Re: incrementable voltage counter

 

Won't those make for far too many devices compared to Henry's circuit?


Vlad
______________________
-- holding, among others:
a universal analog/digital filter, block-level models
for power electronics (and not only), math blocks
with a more stream-lined approach, some digital
ADC, DAC, (synchronous-)counter, JKflop, etc.
Re: PA10M schematic problem (izzydad2000)

 

I think he replied to his own upload that he managed to fix it, it doesn't appear in normal conversations but in standard "upload" messages. I could be wrong, though.


Vlad
______________________
-- holding, among others:
a universal analog/digital filter, block-level models
for power electronics (and not only), math blocks
with a more stream-lined approach, some digital
ADC, DAC, (synchronous-)counter, JKflop, etc.
Re: incrementable voltage counter

 

Why not a couple of flip-flops (in a cascade counter) and an R-2R ladder?

Jim Wagner
Oregon Research Electronics

On May 19, 2014, at 9:59 PM, helmutsennewald@... [LTspice] wrote:

?

Hello Henry,
Sorry, I forgot it's only a divider, but not a counter.
Now I recommend to simply use a chain of D-flipflops for a counter with binary outputs.

The mentioned example "A_counter_test.asc" had mistakes with the symbol and the comment.
I have uploaded a corrected example "A_counter_test.asc"-

Files > Tut > Digital A-Devices > A_counter_test.asc

?
Best regards,
Helmut
Re: Current Step Algorithm

 

Hello Henry,

Any flipflop needs a parameter Td and/or Trise. I have mentioned this many times in this forum.

Best regards,
Helmut
Re: incrementable voltage counter

 

Hello Henry,
Sorry, I forgot it's only a divider, but not a counter.
Now I recommend to simply use a chain of D-flipflops for a counter with binary outputs.

The mentioned example "A_counter_test.asc" had mistakes with the symbol and the comment.
I have uploaded a corrected example "A_counter_test.asc"-

Files > Tut > Digital A-Devices > A_counter_test.asc

?

Best regards,
Helmut
Re: Current Step Algorithm

ehydra
 

I don't think I have the whole overview what do you want!

I hopefully don't be killed by bullets from Mike...
Here this circuits counts up three-times and then down twice controlled by input CLK and DIR and the dynamic count status is a single voltage output:


You can now modify my idea in musings...

A DFF without td is a bad idea. Sometimes it didn't work. I have no clue what is the reason.

If you don't need exact voltage/current steps you can use idt().

Have fun!
- Henry


tindelsurf@... [LTspice] schrieb:

Hi...
I'm trying to get a behavioral current source algorithm to increase or decrease the amount of current every 1ms based on a window comparator. I have a couple D-FF's with 0 prop delay and it's working, but the simulation is SLOW about 10 minutes for 500ms simulation.... I'm trying to speed it up a bit.
Right now I have:
I=if(v(rise_edge)==1,if(v(count_up)==1,I(B3)+0.5,if(v(count_down)==1,I(B3)-0.5,I(B3))),I(B3))
where V(rise_edge) is a D-FF rising edge detector with 0 prop delay and 0 rise time.
V(count_up) and V(count_down) is the output of a window comparator that is typically sent to a FPGA and the FPGA increases or decreases the current.
I(B3) is the behavioral current source
Any other bright ideas on how to sense the rising edge and count up or down only once on the rising edge of the clock (or every 1ms of simulation?)
Re: incrementable voltage counter

ehydra
 

Hi Helmut -

And it counts 0, 1, 2, 3 at the output line? I cannot see this functionality.

- H.


helmutsennewald@... [LTspice] schrieb:

Hello Henry,
There is an A-device counter in LTspice. See the example "A-device_counter.asc" from the link below.
Re: incrementable voltage counter

ehydra
 

Look for counter_3.zip !

- H.


Vlad imbvlad@... [LTspice] schrieb:

Speaking of which, it seems that the AND gate cannot be used by renaming
AND to COUNTER (and using cycles/duty). Still, it's a shame it doesn't have
incremental voltage at the output.
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