I think a positive real td is implicit here because if not the CLK input can't be a clock. One of it's phase would be removed and the signal would be static thereafter.
Or?
- H.
Vlad imbvlad@... [LTspice] schrieb:
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I forgot to say it: you should add one of
td/trise/tfall/tau/[Rout,Cout] (as Helmut reminded recently) to at
least one of the A devices and the inverter. As it is now, it works
but, because of the loop, it may cause problems in larger circuits.
This is similar to the DFLOP problem: if td=0 then _Q and D will have
the same states, but _Q needs to change because of D, hence the "time
step too small" errors.
