Yes, I read all the advice and started out with a very low value for CSHUNT, but ended up with 5pF in order to get convergence. However, this was BEFORE I added the LT1375. Rather than a proper SMPS I was initially working with a switched load on the PTC, and then a Heath-Robinson arrangement of switches and pulse generators set up to do something SMPS-like in the simplest possible way, because the regulator I'm actually using (MCP16331T-E/CH) doesn't appear to have a SPICE model. So 5pF was not unreasonable. If I had stuck with 1e-15 I would still be tearing my hair out. However, having made some progress and achieved something that didn't look completely wrong, I then went on a search for something a bit like a MCP16331T-E/CH that had a model, in order to move a little closer to reality. I was not surprised to find I now had convergence problems again, but this time no matter what I did I either got no convergence at all, or LTSpice slowed to a crawl. But with CSHUNT removed and the timebase shift, I now have all six SMPS's working with the PTC in place, and I can see that it should pass the formal inrush current test by a significant margin, even though strictly speaking it doesn't have to (if the customer asks you to jump a hurdle, and doing so wont kill you, you jump the hurdle). Apart from the capacitor oddity, the model is now stable against changes. And yes, when I replaced one big capacitor with several capacitors in parallel I used ideal capacitors, not capacitors with parasitics. I might try again now I've made various changes.
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Regarding voltage/current sources, I gave the voltage source a series resistor. From what I've read, LTSpice will convert such voltage source to the equivalent current source before modelling commences, so I didn't do that manually.
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On Thu, Feb 27, 2025 at 10:42 AM, Andy I wrote:
Sorry, I misunderstood:
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On Thu, Feb 27, 2025 at 01:25 PM, eetech00 wrote:
The "LT" characters get an overbar.
That is not a new bug in 24.1.4.? The fact that the schematic editor displays it with the overbar, that is.? It has "always" worked that way, I think ever since LTspice had that feature that preceding anything with an underscore (under certain conditions that you listed) causes it to display in the schematic editor with an overbar.
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Oh...I would think they would fix that in this version
?
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But the command executes correctly, right?? Or does v24.1.4 mess that up too?
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The command works right, just looks weird.
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Yes, it is a bit annoying that the underscore always causes the word after it to have the overbar when seen in the schematic editor.? I took it as a relatively minor annoyance.
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Anyway, I think nothing about this has changed in version 24.1.4.
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Andy
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Ok
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On Thu, Feb 27, 2025 at 10:31 AM, Andy I wrote:
Does it work to put the filenames in quotes?? As a temporary workaround.
Hi Andy
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No...it doesn't seem to matter.
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I also discovered if the statement is changed to a comment, the behavior is the same.
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Sorry, I misunderstood:
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On Thu, Feb 27, 2025 at 01:25 PM, eetech00 wrote:
The "LT" characters get an overbar.
That is not a new bug in 24.1.4.? The fact that the schematic editor displays it with the overbar, that is.? It has "always" worked that way, I think ever since LTspice had that feature that preceding anything with an underscore (under certain conditions that you listed) causes it to display in the schematic editor with an overbar.
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But the command executes correctly, right?? Or does v24.1.4 mess that up too?
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Yes, it is a bit annoying that the underscore always causes the word after it to have the overbar when seen in the schematic editor.? I took it as a relatively minor annoyance.
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Anyway, I think nothing about this has changed in version 24.1.4.
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Andy
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Re: Issues running LTspice as a batch service
I tried putting all the symbols under the same folder as the simulation. Let me try to better describe what I am doing.
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A python service is polling an AWS message queue for incoming instructions to run a job. The message has the location of a simulation file in AWS S3. Python pulls the .asc file and kicks off LTspice with the provided command line interface using this line of code?
process = await asyncio.create_subprocess_exec(LTSPICE_PATH, "-b", "-run", solverFlag, fpath, stdout=asyncio.subprocess.PIPE, stderr=asyncio.subprocess.PIPE)
*NOTE* -b for batch mode, no interactive gui
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That code kicks off LTspice as an async process. I have a callback function which runs when the process finishes that zips up the output files and places them back into AWS S3. The user is then emailed the status of their job and the location of their files.
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All of this works great!
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What isn't working is when I try to run this process as a windows service. The python is running properly but kicking off LTspice results in this error code 3221226505 so I get an email saying "Simulation failed with status code 3221226505".
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Since there is no descriptive error message I have no idea why everything works fine when I run it while I'm logged in but it won't run as a background service. I need it to run as a background service because the server won't let a user stay logged in indefinitely.
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Does it work to put the filenames in quotes?? As a temporary workaround.
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I'm guessing it's a bug caused by changing the code for labeling nets/pins with the overbar, meaning "NOT".
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Analog Devices needs to learn to leave things alone when they work.
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Andy
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If I add .inc/.lib statement on schematic:
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.inc file(3)_LT.txt
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It is converted to:
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.inc file(3)(overbar)LT.txt
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The "LT" characters get an overbar.
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Seems if a parenth, bracket, curly brace is preceded by an underscore, the followed text gets an overbar.
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I've never tried it with a switcher, but once
I looked at the ripple voltage and current at the reservoir
capacitor of a simple power supply, and saw what appeared to be
a 'ghost' of the series inductor (limiting inrush current) on
the AC side affecting the phase angle. Changing the inductor
value changed the phase a bit. This 'ghost' inductance might
series resonate with the lossless capacitor so as to produce
oscillations. Could be worth investigating.
On 2025-02-27 17:29, eewiz via
groups.io wrote:
For resevoir and pump capacitors in switchers, I have found
that adding ESR close to reality for the capacitor type, size
and capacitance makes things better.
I have also found that adding some milliohms to model trace
resistance in to and out of switchers helps.
--
OOO - Own Opinions only
If something is true:
* as far as we know - it's science
*for certain - it's mathematics
*unquestionably - it's religion
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For resevoir and pump capacitors in switchers, I have found that adding ESR close to reality for the capacitor type, size and capacitance makes things better.
I have also found that adding some milliohms to model trace resistance in to and out of switchers helps.
If you are using 0V voltage sources to monitor input and output currents, series resistance can be added within each voltage source.
Even if you have only one bulk resevoir cap you can use five 0V sources, one for each switcher, to monitor the current into each switcher.
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All for now
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Sent:?Thursday, February 27, 2025 at 9:58 AM
From:?"Robert via groups.io" <birmingham_spider@...>
To:[email protected]
Subject:?Re: [LTspice] LTspice XVII error work around #Time-step-too-small
Yes, I did try setting the maximum timestep, and all the other things in the FAQ. I also tried tweaking the circuit (same function, different way of achieving it), but as eewiz has found that just moved the problem to another random part of the circuit. Nothing I tried solved the problem, until I shifted the time base. Of course that could just as equally create a problem where none existed, as may the other fixes, but why would you go out of your way to create a convergence problem? As for models being "dodgy", well that is inevitable when a component behaves in a complicated way. A PTC fuse has only two legs and a simple task to perform, but in modelling terms its behaviour is complicated. Add in a monolithic SMPS, and there is even more to go awry when modelling.
?
Later this morning I added the remaining five SMPS's. I would like each to have its own reservoir cap, so I can measure the DC current each contributes, but that just results in a convergence failure. So I'm having to live with them sharing one big capacitor in the model.? ?Same (perfect) capacitance in the same electrical location, but one way of achieving that works and the other doesn't.
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On Thu, Feb 27, 2025 at 09:58 AM, Robert wrote:
Later this morning I added the remaining five SMPS's. I would like each to have its own reservoir cap, so I can measure the DC current each contributes, but that just results in a convergence failure. So I'm having to live with them sharing one big capacitor in the model.? ?Same (perfect) capacitance in the same electrical location, but one way of achieving that works and the other doesn't.
Let me see if I understand.? You have 3? 5 or 6 ideal capacitors connected in parallel, which fails?? And when replaced by one ideal capacitor with the same total capacitance, it doesn't?
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I just want to make sure you did not accidentally select capacitors from LTspice's "Select Capacitor" menu.? All the capacitors in that menu are complex models for real (purchasable) capacitors, including parasitics.? They aren't ideal.? I'm assuming you didn't do that.
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So let's say the capacitors you used really were ideal.? Of course it should not have made any difference whatsoever.? The fact that it does, suggests that you are right on the hairy edge of instability, and even the slightest change in matrix element calculations, caused one version to fail.? Could have gone either way.
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Andy
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On Thu, Feb 27, 2025 at 07:04 AM, eewiz wrote:
Also, I often find that reducing the tolerance values of trtol, abstol, vntol and chgtol help convergence and to reduce the likelyhood of SM, TS or femtosecond pace issues as a circuit grows.
You probably meant to say that you increased the tolerance values.? But you did that by making the magnitude of their negative exponents smaller, right?? So it's confusing to keep it straight, which way they went.? :-)
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Decreasing them would have set their tolerances even tighter, which could be good for ultimate accuracy but bad for avoiding convergence failures.
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Andy
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On Thu, Feb 27, 2025 at 04:20 AM, Robert wrote:
Regarding my own fight with this problem, I can model the LT1375HV on its own, and I can model the PTC fuse on its own, but when the two are combined I get convergence problems
FYI, that is not unusual.? Combining models into the same simulation is often what causes misbehavior to rear its ugly head.? It's just how things often go.
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Another thing you might consider, is changing your own models to avoid voltage sources, such as your PWL voltage source.? SPICE is happier with current sources, even to the point where a Norton equivalent circuit is less likely to lead to problems than its Thevenin equivalent, even though we know they are "identical".? They aren't - well, in SPICE they aren't.? (This is not just an LTspice thing.)
?
Andy
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On Thu, Feb 27, 2025 at 04:20 AM, Robert wrote:
5pF is not unreasonable for the circuit I'm modelling,
Keep in mind, 5pF will be added to every single node in the circuit.? If you have an IC, which it appears you do (LT1375HV, maybe others), then it is added to every internal node of those models too.? It could significantly alter the simulation.
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Helmut's recommendation in the FAQ file was CSHUNT = 1e-15, and not larger.? That is 1 fF (femtoFarad), or 0.001 pF.? He also noted: "Be very careful with this option. It may disturb your circuit."
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IMO, 0.5 pF is not unreasonable for external pins that land on PCB pins (oops!) pads, but it is much too large for anything internal.? Also remember that many most SPICE models are not physical, and disturbing an internal node like this might change its calculations significantly.
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Andy
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Thanks Andy and Tony.
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Got it and appreciate the replies.
All the best,?
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Alan?
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alan,
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I don't think you can add more than what LTspice gives you already in those plots.? There is no option to change the "Quantity Plotted" on the right axis, so no, you can't "hack" it to add something else.? In .AC analysis it insists on having the left and right axes that way.
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Of course you can plot S21 and SWR in separate plot panes, which might be a better way to handle it.? ?(My LTspice is set up to use Vertical window tiles, which helps a bit.)
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Andy
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Indeed, it is troubling to wonder exactly what is meant by asking when a signal is "< 2V".? That happens continuously, after the signal crosses below 2.0 V.? Surely you would not want the .MEAS command to spit out volumes of data for every possible time value from that point forward.? (There are infinitely many, after all.? Try fitting THAT in your .LOG file.)
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IMO, that is one of the many things that causes much grief and confusion about the .MEASURE syntax.? Well, for me it is.
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That is not LTspice's fault.? The .MEASURE command evolved over years (decades?) before there was an LTspice, so LTspice inherited the varied and confusing syntax that was already out there.
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Also, for syntax sticklers, the fact that the .MEASURE command uses the assignment operator ("=") as if it were a comparison operator (should have been "==") is a little bit troubling.? But that is life and it is what it is (we have to accept it).? LTspice can't "fix" syntax mistakes without breaking it for thousands of existing SPICE users.
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FYI, changing the "Quantity Plotted" is not a normal feature that everyone needs to know and understand.? It is one of those "rarely used" things that occasionally comes in handy, but you are not likely to know until then, and maybe never.
?
Andy
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On 27/02/2025 16:10, alan victor via
groups.io wrote:
Yes, I tried. All I get are selections on GD and phase.
Only for Bode. If you choose the Cartesian format, you can get
imaginary. what other options do you want?
?
For example, in using the s parameter script it would be nice
to plot transmission gain s21 and SWR (for which I have a simple
expression) on left and right axis of a single plot pane. Are
there more plot options if I rev up from LTspice XVII?
S-parameters of 1 and 2 port networks are automatically available as
plot options if you use the .NET directive with .AC analyses. This
then gives you the options: Sxx, Yxx, Zxx, Zin & Zout.
See: Help > LTspice > LTspice? > Dot Commands > .NET ¡ª
Compute Network Parameters in a .AC Analysis
For SWR and other formats like Gmax and MSG, I have defined plot
functions, which are stored in the plot.defs file. Hardly anyone
actually uses plot.defs, but it's very useful once you get used to
it.
E.g.:
* Functions for RF design using S-parameters with 2 port networks
* Note: due to the way LTspice displays functions (as voltages), MSG
& Gmax are exported as square roots since they are powers to
start with
.func mS11() {mag(S11(V1))}
.func mS21() {mag(S21(V1))}
.func mS12() {mag(S12(V1))}
.func mS22() {mag(S22(V1))}
.func DeltaInt() {S11(V1)*S22(V1)-S12(V1)*S21(V1)}
.func MSGInt() {ms21()/ms12()}
.func KR()
{(1-ms11()**2-ms22()**2+mag(DeltaInt())**2)/2/mag(S21(V1)*S12(V1))}
.func GmaxInt() {1/(Kr()+sqrt(Kr()**2-1))*MSGInt()}
.func MSG() {sqrt(MSGInt())}
.func Gmax() {sqrt(GmaxInt())}
.func VSWR(Sxx) {(1+mag(Sxx))/(1-mag(Sxx))}
(Functions including "Int" are not for plotting, they are
intermediate functions.
Note: if you edit plot.defs (Plot Settings > Edit Plot Defs
file), the changes don't become active until LTspice is closed and
re-started.
--
Regards,
Tony
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Thanks Tony.?
?
Yes, I tried. All I get are selections on GD and phase.?
?
For example, in using the s parameter script it would be nice to plot transmission gain s21 and SWR (for which I have a simple
expression) on left and right axis of a single plot pane. Are there more plot options if I rev up from LTspice XVII??
?
All done in simple AC analysis, so X axis is frequency.?
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Yes, I did try setting the maximum timestep, and all the other things in the FAQ. I also tried tweaking the circuit (same function, different way of achieving it), but as eewiz has found that just moved the problem to another random part of the circuit. Nothing I tried solved the problem, until I shifted the time base. Of course that could just as equally create a problem where none existed, as may the other fixes, but why would you go out of your way to create a convergence problem? As for models being "dodgy", well that is inevitable when a component behaves in a complicated way. A PTC fuse has only two legs and a simple task to perform, but in modelling terms its behaviour is complicated. Add in a monolithic SMPS, and there is even more to go awry when modelling.
?
Later this morning I added the remaining five SMPS's. I would like each to have its own reservoir cap, so I can measure the DC current each contributes, but that just results in a convergence failure. So I'm having to live with them sharing one big capacitor in the model.? ?Same (perfect) capacitance in the same electrical location, but one way of achieving that works and the other doesn't.
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On 27/02/2025 15:38, alan victor via
groups.io wrote:
Right side of plot window is assigned to phase.?
?
Anyway to "hack" and assign right side of plot window?
to another parameter??
(This only applies to plots in the frequency domain.)
Did you try to change it?
If you bring the cursor close to the left axis, its appearance will
change to a ruler. You can right-click and you will get a dialogue
where you can change the quantities plotted: Bode, Nyquist or
Cartesian.
For Bode, you can choose either phase or group delay, or none, by
right-clicking on the right axis.
--
Regards,
Tony
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John Woodgate
eewiz
Tony Casey