--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:
--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:
--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:
Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.
I will try the cap idea and see how it works out.
Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.
Clear- thanks for pointing that out. I'll give it a try.
My problems are still with me.
I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.
