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I have some files that ran ok in simulation a few months ago.

I moved everything to a folder on my desktop, but leaving the library in the the same folder as the LTSice executable ( program86 folder in windows). I've done this to ease back up etc.

Some of my files still seem to run ok ( transient analysis), but others won't run - ie I get a few hundred nano seconds of simulation and everything grinds to a halt. I tried using different transistors types, still no joy. Interestingly, the loop gain simulations run ok. Weird.

Any ideas as to what could be the problem? I've set everything in the tools tab to default. BTW.

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

I have some files that ran ok in simulation a few months ago.

I moved everything to a folder on my desktop, but leaving the library in the the same folder as the LTSice executable ( program86 folder in windows). I've done this to ease back up etc.

Some of my files still seem to run ok ( transient analysis), but others won't run - ie I get a few hundred nano seconds of simulation and everything grinds to a halt. I tried using different transistors types, still no joy. Interestingly, the loop gain simulations run ok. Weird.

Any ideas as to what could be the problem? I've set everything in the tools tab to default. BTW.

Hello Jason,

Please reset your SPICE settings.

Control Panel -> SPICE-> Reset to default

If it still hangs in .TRAN, you could try with the cshunt option.

.options cshunt=1e-16

It adds a capacitor from every node to GND.
Be warned. If you have too much cshunt, your circuit will
become much different from your design.

Best regards,
Helmut

jason.vanryan <andrewc.russell@...> wrote:

I have some files that ran ok in simulation a few months ago.

LTspice is continually being updated and improved. It's possible a
simulation that barely got by before, has a problem now due to a subtle
change. I don't have any specifics, just saying that it's possible.
Unfortunately, without a side-by-side comparison, you can't say for sure.

I moved everything to a folder on my desktop, but leaving the library in

the the same folder as the LTSice executable ( program86 folder in
windows). I've done this to ease back up etc.

Moving files could cause the simulation to bring in a different model than
before. Any change is susceptible to error.

Some of my files still seem to run ok ( transient analysis), but others

won't run - ie I get a few hundred nano seconds of simulation and
everything grinds to a halt. I tried using different transistors types,
still no joy. Interestingly, the loop gain simulations run ok. Weird.

The loop gain simulations use .AC analysis. AC analysis is inherently
simpler because what is simulated is 100% linear; and most of the problems
that cause transient analysis to get stuck, are due to nonlinear things
that are ill-behaved (such as discontinuities in a function or its
derivative).

Any ideas as to what could be the problem? I've set everything in the

tools tab to default. BTW.

Were you using the defaults before?

Sometimes the Alternate Solver helps.

Sometimes loosening up on ABSTOL (making it less small, i.e., a
less-negative exponent) and/or RELTOL can help, but this can affect
accuracy.

Various other control panel options may sometimes help too.

Regards,
Andy

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

I have some files that ran ok in simulation a few months ago.

I moved everything to a folder on my desktop, but leaving the library in the the same folder as the LTSice executable ( program86 folder in windows). I've done this to ease back up etc.

Some of my files still seem to run ok ( transient analysis), but others won't run - ie I get a few hundred nano seconds of simulation and everything grinds to a halt. I tried using different transistors types, still no joy. Interestingly, the loop gain simulations run ok. Weird.

Any ideas as to what could be the problem? I've set everything in the tools tab to default. BTW.

Thanks for the feedback. This is happening on the latest version I downloaded and after I hav set all sim variables to default in the tool tab.

I will try the cap idea and see how it works out.

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

--- In LTspice@..., "analogspiceman" <analogspiceman@...> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

Hello Jason,

Please try my suggestion with cshunt as I mentioned before.

Best regards,
Helmut

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

Can you change the circuit step by step so that you can see which modification causes the problems?

Best regards,

Frank

--- In LTspice@..., "Helmut" <helmutsennewald@...> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

Hello Jason,

Please try my suggestion with cshunt as I mentioned before.

Best regards,
Helmut

Hello Helmut,

I did try that - 1e-12 and 10e-12 still no success

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

--- In LTspice@..., "Helmut" <helmutsennewald@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

Hello Jason,

Please try my suggestion with cshunt as I mentioned before.

Best regards,
Helmut

Hello Helmut,

I did try that - 1e-12 and 10e-12 still no success

Hello Jason,
I never use higher cshunt values than 1e-15.

You could send me one of your designs if you can't upload it
for some reason. I would then try on it.

Best regards,
Helmut

--- In LTspice@..., "Helmut" <helmutsennewald@...> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "Helmut" <helmutsennewald@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

Hello Jason,

Please try my suggestion with cshunt as I mentioned before.

Best regards,
Helmut

Hello Helmut,

I did try that - 1e-12 and 10e-12 still no success

Hello Jason,
I never use higher cshunt values than 1e-15.

You could send me one of your designs if you can't upload it
for some reason. I would then try on it.

Best regards,
Helmut

Sure, where can I send it (email address). I would appreciate your help on this.

jason.vanryan <andrewc.russell@...> wrote:

< long unnecessary block of un-trimmed previous replies to replies to
replies >

Sure, where can I send it (email address). I would appreciate your help on

this.

I would first try uploading the schematic(s) to the group's website.
That's what we encourage people to do when they want help. See the
instructions on the group's website for what directory to upload them into.
(Group's website is: )

If you are unable to upload your files (I don't know why anyone would be
unable to), or if for security reasons you don't want them to be visible by
all members of this group, then use Helmut's offer to email them to him
directly. His email address is at the top of any message he sends to the
group. If for some reason you are unable to see that, it is: helmutsennewald
(at) yahoo.com .

Andy

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

--- In LTspice@..., "Helmut" <helmutsennewald@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "Helmut" <helmutsennewald@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

Hello Jason,

Please try my suggestion with cshunt as I mentioned before.

Best regards,
Helmut

Hello Helmut,

I did try that - 1e-12 and 10e-12 still no success

Hello Jason,
I never use higher cshunt values than 1e-15.

You could send me one of your designs if you can't upload it
for some reason. I would then try on it.

Best regards,
Helmut

Sure, where can I send it (email address). I would appreciate your help on this.

Hello,

Haven't you see the email address on every of my messages?

helmutsennewald@...

Best regards,
Helmut

This problem is solved now. Thanks for your input. The problem is I was using the old Fairchild KSA and KSC models for the 3503 and the 1381. I replaced these with a different transistor and the sim ran ok. Then I replaced just the one back to the original device, it ran, but it was wrong.

I found some updated models on the web that have solved it.

I also understand that Fairchild have updated these models now, so they should converge.