Andy wrote:
So what I'm asking is this. How do I get a visual representation of the
components MINUS the *.asy file. And I don't care how many steps it
might take. Might even write a converter program if there isn't a way
to do this inside ltspice.
It is not done by LTspice. (LTspice needs no schematic representation
of what a circuit or subcircuit looks like ... the SPICE netlist has
everything it needs.)
Yes, but not everything *I* need.
It is NOT trivial to convert a netlist of one form or another, into a
human-readable schematic.
Not talking about a netlist.... I don't think. (???) Talking bout a literal *.asy file which should have all the info in it necessary to make some kind of representation of as a schematic -- even if it's an IC block with 100 pins all on one side. the sym file can be modified.
The question has been asked here a few times before. Some research
has been done, and some of the previous discussions touched on some of
that research and a few other programs that offer such capability.
Try searching through the group's archives for those earlier message
threads.
Ouch.
Many IC models are macro-models and contain functional equivalents for
whole blocks of circuitry. Some IC macro-models don't even contain a
single transistor! And that can give rise to various problems.
Nope. Not a problem. Those can be replaced by actual transistors once the connections are identified.
Depending on what you are looking for, a full schematic may not be
needed. It might be possible to trace out everything connected to the
input pin in question, and get a better handle on why it behaves the
way it does. Note: it may not be pretty what you discover about the
subcircuit; many subcircuits are poorly constructed and/or used
improperly!
Andy
(PS: I'll bet that some of us SPICE oldtimers got to be pretty good at
turning SPICE netlists into hand-drawn schematics, for those times
when we really needed to know what a circuit looks like.)
If I could see before/after shots of a couple of them I'd have something to start with. As it is, I'm just getting up to speed on the "heirarchy"
file.asc (top)
|-- file.asy (schematic)
`-- top.sub (external assembly of .model's)
Currently wobbly but ok with *.asy, and completely flummoxed by *.sub. which I'd like to be able to convert to/from.
Thanks for the reply Andy! :-)
And no... not going to search old message in this forum. Yow! Having enough probs identifying a small realistic set of good cheap transistors, especially for driver and power output for an audio amp.
