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I uploaded "Hierarchy_netnames.zip" which illustrates how the netnames change due to context.? It has five instances of lower-level schematics, each consisting of one resistor.? The pins connect to its symbol, and from there to nets on the top-level schematic.? LTspice "connects" them by making their netnames the same, so they are truly ideal connections with zero added resistance.

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(1)? Open MyRes1.asc, one of the lower-level schematics.? Hover over the top net and see that its netname in this view is "Top".? The context here is in isolation, not part of the main simulation.

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(2)? Then open Top_Level.asc which is the top-level schematic.? Now right-click on the X1 symbol and click "Open Schematic".? This opens that particular instance (X1) of MyRes1.asc.? Hover over the top net.? Notice its netname has changed from "Top" to "AAA".? It inherited the netname from the top-level schematic.? That is what happens whenever a subcircuit or a lower-level schematic is connected to nets in the next higher schematic.? The netnames in the lower-level schematic effectively change to match those of the higher schematic.

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This is where context matters.? By opening MyRes1.asc in isolation (by double-clicking on it in Windows Explorer), it has no context, and it must use the netnames printed on that schematic even though they will not be used.? By opening MyRes1.asc from the top-level schematic, you have given it context.? You have chosen that one instance (X1) of that lower-level schematic, and LTspice rewards you by showing the adjusted netnames as they exist in the main circuit.

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(3)? Open MyRes3.asc from Windows.? Hover over the top and bottom nets and note their netnames.? The upper netname is "Top" and the lower netname is 0 or ground.? That is correct in this context because connections have not been made to any other schematic's nets.? Those are temporary netnames.

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(4)? Now open Top_Level.asc again.? Do these steps in this order:

(LTspice has a wee synchronization issue, making it necessary to do these steps in this order.)? The former "Top" net has inherited the netname "DDD" from the Top_Level schematic.? The bottom netname is no longer ground!? It has inherited the netname "EEE" from the Top_Level schematic, replacing node 0.

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Like I say, context changes everything.? By viewing the schematic of that one instance (X3) of the lower-level schematic, you see what the netnames change to.? What you thought was ground, is now a different net, named "EEE".? That is true only in this context.? Without context, the lower net looked like ground, which was a temporary netname.? Context is everything.

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What's going on is basically this:? On lower-level schematics or in subcircuits, expanding the SPICE netlist causes every net that goes to a pin to have its netname changed.? All of them inherit the netnames of the nets they connect to in the next higher hierarchy level.? LTspice does that uniformly, making no exception for node 0 - even node 0 changes to another name.? You see that only in the context where it is part of the top-level schematic.? Without that context, it appears to be ground, but that was just a place-holder.

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I was wrong about something.? I thought that if you left the net not connected to anything in the top-level schematic, it would revert to ground.? But alas, it does not.? Even floating pins without wires have netnames, and it picks up that netname instead of defaulting to ground.? Therefore, the usefulness of grounding a net on a lower-level schematic, and simultaneously bringing it out on a pin that can go somewhere else, seems awfully limited -- to the point that I don't see very much reason for doing that.? I can envision a few reasons to do it anyway, to modify one schematic to use as a lower-level block without making extensive manual edits.? But?it seems not useful to draw a new schematic that way.

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I hope some of this makes sense.

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Andy

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