Keyboard Shortcuts
ctrl + shift + ? :
Show all keyboard shortcuts
ctrl + g :
Navigate to a group
ctrl + shift + f :
Find
ctrl + / :
Quick actions
esc to dismiss
Likes
- Softrock40
- Messages
Search
Re: SR-40 DDS
KD5NWA
You mean this;
< > I know I have posted it several times, will work with DDS since the output is symmetrical. At 10:44 PM 10/26/2005, windy10605@... wrote: I was just sitting here thinking (1000mi away from my hobbybench). Since the Tayloe detector is really a divide by two, the purpose of the first 74HC74 is just to give you a good 50% duty cycle for the clocking to give you the proper 90 degree phase shifts (but it also cuts the frequency in half). Those of us wanting to try out the AD9850 DDS means an output of 60Mhz to achieve a good receiver for 20m. 60Mhz is a stretch for the AD9850 (max input osc frequency, max voltage of 5V, consumes max power, runs hot, etc). For the 3.3V AD9850 40Mhz analog out is about it. What if you took a 30MHz analog signal, ran it through the termination resistance for voltage --and then-- through a full wave bridge into a 5 pole or 7 pole LPF and into the comparator as shown in one of AD'd app notes. The idea is that the full wave bridge using matched, high speed, signal diodes would effectively double the frequency. You adjust the comparator reference voltage to give you two good clock signals for every sine wave from tha DAC. Duty cycle is not important since the 74HC74 cleans that up (at half the frequency). DDS output 30Mhz sine, bridge output 60Mhz full wave rectified, comparator output 60Mhz clock string, "cleaner upper"Cecil Bayona KD5NWA www.qrpradio.com I fail to see why doing the same thing over and over and getting the same results every time is insanity: I've almost proved it isn't; only a few more tests now and I'm sure results will differ this time ... |
Re: QSD Models
Tony Parks
Hi Phil,
toggle quoted message
Show quoted text
The question I just ask about gain reduction as a function of phase clock skew is not the right question to ask. What we really are interested in is the gain from RF input to demodulated signal output. In the case of CW I would think this would just be the vector sum of the I and Q signals. Another important question is if clock skew causes undesired signal response. 73, Tony KB9YIG ----- Original Message -----
From: "Phil Covington" <p.covington@...> To: <softrock40@...> Sent: Wednesday, October 26, 2005 1:04 PM Subject: [softrock40] QSD Models Hi all, |
Re: QSD Models
Tony Parks
Hi Phil,
toggle quoted message
Show quoted text
I wonder if you would have time to run your simulation again for the two switch case? What I would like to understand is the sensitivity of the QSD gain to changes in the phase relationship between the sampling pulses. If the sampling pulses are not exactly 90 degrees apart (25ns), how quickly does the gain fall off? 73, Tony KB9YIG ----- Original Message -----
From: "Phil Covington" <p.covington@...> To: <softrock40@...> Sent: Wednesday, October 26, 2005 1:04 PM Subject: [softrock40] QSD Models Hi all, |
Re: SR-40 DDS
Here's my understanding of the I and Q representation. You have to sample at 90 degrees apart in order to resolve the properties (modulation) of the Carrier frequency. Therefore you always have to sample at four times the desired carrier. Think of it as an X and Y coordinate system. If the X and Y axis are not 90 degrees apart, you have a difficult time resolving the resultant vector. Now you can do the whole job with the first and second samples out of four. You could actually throw away the third and fourth samples. However if you subtract the third sample from the first sample and you subtract the fourth sample from the second sample you get a differential input which removes any DC offset and some of the noise. Bottom line is that I and Q must be 90 degrees apart. From that information you can derive the amplitude, phase, and any rate of changes involved. FM is related to the rate of change of the phase angle of the I and Q. Amplitude is the square root of the sum of the squares of the I and Q. Phase angle of the carrier is the arc tangent of I/Q. And so on. Now you can see the importance of maintaining a 90 degree or 25% sampling rate for I and Q over all frequencies of interest. There in lies the beauty of the digital divide by 4 perhaps using the two 7474 flip flops. Another approach is to use synchronous J-K flip flops or hopefully a FPGA (Field Programmable Gate Array) some day. There is a 25 MHz limit on the clock speed of some 7474 flip flops. I have seen other 7474's that will clock at 100MHz. However there is an upper limit on the Soft Rock 7474 FF's which might come into play some day. So far we don't seem to have hit it :-)
toggle quoted message
Show quoted text
Just one more thought. Sampling at the carrier frequency (or four times the carrier frequency) is the equivalent of multiplying (or hetrodyning) the carrier times the sample rate. This is a Direct Conversion which gives you audio frequencies at the modulation rate after low pass filtering. We are exploring the DSP chips available to concentrate on this filtering and demodulation. There in lies the beauty of the Software Defined Radio. How we filter I and Q and then mathematically demodulate I and Q is the secret to performance. I'm really digging this project, too :-) Thanks for the bandwidth :-) Regards, John windy10605@... wrote: I was just sitting here thinking (1000mi away from my hobbybench). Since the Tayloe detector is really a divide by two, the purpose of the first 74HC74 is just to give you a good 50% duty cycle for the clocking to give you the proper 90 degree phase shifts (but it also cuts the frequency in half). Those of us wanting to try out the AD9850 DDS means an output of 60Mhz to achieve a good receiver for 20m. 60Mhz is a stretch for the AD9850 (max input osc frequency, max voltage of 5V, consumes max power, runs hot, etc). For the 3.3V AD9850 40Mhz analog out is about it. What if you took a 30MHz analog signal, ran it through the termination resistance for voltage --and then-- through a full wave bridge into a 5 pole or 7 pole LPF and into the comparator as shown in one of AD'd app notes. The idea is that the full wave bridge using matched, high speed, signal diodes would effectively double the frequency. You adjust the comparator reference voltage to give you two good clock signals for every sine wave from tha DAC. Duty cycle is not important since the 74HC74 cleans that up (at half the frequency). DDS output 30Mhz sine, bridge output 60Mhz full wave rectified, comparator output 60Mhz clock string, "cleaner upper" --
Regards, John ========================================================= email: k5jhf@... photos: files: web page: call sign: K5JHF ========================================================= |
Re: QSD Models
Tony Parks
Hi Phil,
toggle quoted message
Show quoted text
The four switch QSD circuit you simulated integrates signal on four capacitors with two of the capacitor voltages summed to form the I or Q signal output. Thus it make good sense that when you simulate a two switch QSD each of the outputs will be cut in half, thus a 6dB gain reduction. The SoftRock QSD circuit uses only two signal integrating capacitors, one each for the I and Q signals. In the v4.0 SoftRock, each capacitor voltage is refreshed two time per cycle and so the gain will be greater than your two switch simulation. Your two switch simulation is correct for the QSD gain of the v5.0 SoftRock. I conclude my observation of a 3dB gain decrease when going from a v4.0 SoftRock to a v5.0 SoftRock is probably valid. Interesting stuff. Thanks for your simulation and SDR software efforts. 73, Tony KB9YIG ----- Original Message -----
From: "Phil Covington" <p.covington@...> To: <softrock40@...> Sent: Wednesday, October 26, 2005 1:04 PM Subject: [softrock40] QSD Models Hi all, |
SR-40 DDS
I was just sitting here thinking (1000mi away from my hobbybench). Since the Tayloe detector is really a divide by two, the purpose of the first 74HC74 is just to give you a good 50% duty cycle for the clocking to give you the proper 90 degree phase shifts (but it also cuts the frequency in half). Those of us wanting to try out the AD9850 DDS means an output of 60Mhz to achieve a good receiver for 20m. 60Mhz is a stretch for the AD9850 (max input osc frequency, max voltage of 5V, consumes max power, runs hot, etc). For the 3.3V AD9850 40Mhz analog out is about it. What if you took a 30MHz analog signal, ran it through the termination resistance for voltage --and then-- through a full wave bridge into a 5 pole or 7 pole LPF and into the comparator as shown in one of AD'd app notes. The idea is that the full wave bridge using matched, high speed, signal diodes would effectively double the frequency. You adjust the comparator reference voltage to give you two good clock signals for every sine wave from tha DAC. Duty cycle is not important since the 74HC74 cleans that up (at half the frequency). DDS output 30Mhz sine, bridge output 60Mhz full wave rectified, comparator output 60Mhz clock string, "cleaner upper"
74hC74 output 30Mhz clock with 50% duty cycle, Tayloe receiver at 15Mhz. I dunno, might work and it would be easier than dual AD9850s ? The more I look at this the more important maintaining the proper phase shift appears to be. it's late............. 73 Kees K5BCQ |
Re: [dds-vfo] Bezel for Hantronix LCD Display
Stan Rife
¿ªÔÆÌåÓý??? Took a look at the SDR-908 page, George. Looks and
sounds fantastic. I can't wait!
?
?
Stan Rife
|
Re: SoftRock software band profiles
Stan Rife
¿ªÔÆÌåÓý??? And THANKS from an end user!!!? I certainly would
not be able to "play", if it weren't for all of you guys talent. Very much
appreciated!!
?
?
Stan Rife
|
Re: SoftRock software band profiles
Stan Rife
¿ªÔÆÌåÓý??? They are probably the same ones that Elecraft uses.
They do maintain a state change even when powered off I
believe.
?
Stan Rife
|
Re: A second Hi-res scan upload to Files - A Multiband SR.
Stan Rife
¿ªÔÆÌåÓý??? That's amazing, Bruce!? I know it took some
planning to get all that in there. How many times did you have to redo it to get
it all in there? Hi Hi
?
Stan Rife
|
Re: [dds-vfo] Bezel for Hantronix LCD Display
George Heron N2APB
Trying to get a neat-looking panel appearance for these ubiquitous LCD displays is always a challenge, but with a little homebrewing care you can achieve pretty decent results.
toggle quoted message
Show quoted text
If you measure carefully, you can have an okay look with the black body of the LCD unit extending a bit from the front panel. As an example, take a look at my prototype "SDR-908" project on the (preliminary) page at . It's not absolutely perfect, but a number of the projects on my workbench never get past this point and they look pretty good. You can take it a step further by making a clear "front panel label", discussed many times in homebrewer circles, using your inkjet printer to print text and graphics on clear acetate material used for overhead projector transparency slides. The trick with the LCD is to mount it flush with the front panel and put a thick black border on the acetate label, surrounding the rectangular display. That's what we did in creating the nice front panel overlay for the Micro908 instrument (). You can leave the clear plastic window in place, thus protecting the LCD surface, or you could use a razor blade to carefully cut out the blank center area for maximum display clarity. 73, George N2APB PS: I cross-posted this because the the topic is useful in the other areas ----- Original Message -----
From: "Mike W" <mike@...> To: "Mark Schreiner" <nk8q@...>; <dds-vfo@...> Sent: Wednesday, October 26, 2005 6:21 PM Subject: Re: [dds-vfo] Bezel for Hantronix LCD Display
|
Re: QSD Models
Hi all,
When you specify a ratio in dB, it is immaterial whether you refer toThis is true only if both voltages are measured across the same impedance. Here is a counter-example: a transformer may have a huge voltage gain, but its power gain is always less then 1. In the case of the QSD circuit, the first voltage is measured across the input impedance of the detector, and the second one is measured on the loading impedance. Phil, does your model allow estimation of these impedances? 73 Alex VE3NEA |
Re: QSD Models
Tony Parks
Quite right Alberto. After I sent the e-mail I realized I had made a wrong statement. dB is indeed dB. (My face is a bit red over that one. :-) )
toggle quoted message
Show quoted text
Thanks, Tony KB9YIG ----- Original Message -----
From: "Alberto I2PHD" <i2phd@...> To: <softrock40@...> Sent: Wednesday, October 26, 2005 3:59 PM Subject: Re: [softrock40] QSD Models Tony Parks wrote:my observations and your simulation are not too different since 3dBTony, |
Re: QSD Models
--- In softrock40@..., Alberto I2PHD <i2phd@w...> wrote:
Tony, Alberto, Of course you are right and thanks for pointing this out. The discrepancy definitely needs to be investigated. 73 de Phil N8VB |
Re: QSD Models
Tony Parks wrote:
my observations and your simulation are not too different since 3dBTony, I beg to differ. Not to be a nit picker, but in the interest of the other group readers who could be misled by that sentence. When you specify a ratio in dB, it is immaterial whether you refer to powers or voltages. A ratio of e.g. 15 dB is 15 dB no matter if you consider voltages or powers. Let's make an example : Suppose the ratio between two voltages is 5:1 i.e. 10V against 2V Computing dBs : 20 * log10(10/2) = 13.9794... dB If those voltages are applied to identical loads, then the power ratio would be (10^2)/(2^2) = 25 Computing dBs : 10 * log10(25) = 13.9794.... dB So tha ratio is still 13.9794... dB, whether you consider voltages or powers. As said, no polemic intent in this message, just to avoid that others can be misled. 73 Alberto I2PHD |
Re: QSD Models
Hi Tony,
I will be definitely interested in hearing the results of your measurement on the v5 circuit. Using an ideal switch, the voltage gain difference between the 2 and 4 switch QSD seems to be exacly 6 dB. Actually the 4 switch circuits shows some gain (for a 25% clk ~ 4dB) while the 2 switch QSD shows a small loss (for 25% clk ~ -2 dB). This is in reference to the input signal normalized to 0 dB. The PowerSDR console's power spectrum is calibrated in dBm so if it showed a difference in 3 dBm it seems like the 6 dB difference in voltage gain predicted in the model would be close? 73 de Phil N8VB --- In softrock40@..., "Tony Parks" <raparks@c...> wrote: was a voltage ratio. Phil's simulation show more on the order of 6 dBdecrease in gain between the four switch and two switch QSD circuit. The two don'twill post what I see.VK6APH, a twohas think theswitch SoftRock showed a 3dB difference between the two units as the casedB since 3dBthen my observations and your simulation are not too different switchratio in power is a 6dB ratio in voltage. QSD circuit on my blog at: |
Re: QSD Models
Tony Parks
To answer my own question. The dB reduction in gain that I observed was a voltage ratio. Phil's simulation show more on the order of 6 dB decrease in gain between the four switch and two switch QSD circuit. The two don't agree properly so something is wrong.
toggle quoted message
Show quoted text
I will be repeating the measurement in a few days with a v5.0 and will post what I see. 73, Tony KB9YIG ----- Original Message -----
From: "Tony Parks" <raparks@...> To: <softrock40@...> Sent: Wednesday, October 26, 2005 2:56 PM Subject: Re: [softrock40] QSD Models Interesting graphs Phil. Your results are similar to what Phil, VK6APH, has |
Re: QSD Models
Tony Parks
Interesting graphs Phil. Your results are similar to what Phil, VK6APH, has reported recently. My observations with a stock v4.0 SoftRock vs. a two switch SoftRock showed a 3dB difference between the two units as indicated by the dBm reading on the PowerSDR panadaptor. Not sure, but I think the dB scale on the SDR is actually indicating signal power. If that is the case then my observations and your simulation are not too different since 3dB ratio in power is a 6dB ratio in voltage.
toggle quoted message
Show quoted text
How are you establishing zero dB in your simulation? Thanks and 73, Tony KB9YIG ----- Original Message -----
From: "Phil Covington" <p.covington@...> To: <softrock40@...> Sent: Wednesday, October 26, 2005 1:04 PM Subject: [softrock40] QSD Models Hi all, |
to navigate to use esc to dismiss