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P.S. I put a model of the capacitorless circuit to my blog at:



73 de Phil N8VB

--- In softrock40@..., "Phil Covington" <p.covington@g...>
wrote:

Hi Phil,

I think that you are correct that we could eliminate the signal
integrating capcitor. One of the circuits that I have been playing
with does exacly as you have described - no C and an active opamp LPF
following it. It is a single switch being driven by a 50 ohm source.
The output of the switch feeds directly into the non-inverting input
of the op amp. If the op amp's feedback resistor is 200 ohms then the
conversion loss of the single switch circuit is exactly equal to what
you get with the single switch circuit using the "sampling capacitor".
This is for a 25% duty cycle clock. If I increase the duty cycle to
50% the loss now decreases. Obviously, the duty cycle of the clock is
changing the output impedance of the switch as seen by the opamp. I
am going to play with it more and report the results.

Hope you had a nice trip.

73 de Phil N8VB


--- In softrock40@..., pvharman@a... wrote:

Phil,

I have built a model of the single switch mixer and get the same

result. The

conversion loss is lowest when the on time is 25%.

I'm curently working on a mathematical model of the mixer to

determine the

reason for this. Going to work on this on the plane home but I have

a feeling

that we may be able to eliminate the C after the switch and use the

amplifier

as a LPF to remove the sum component.

Phil... VU2/VK6APH


Quoting Phil Covington <p.covington@g...>:

--- In softrock40@..., KD5NWA <KD5NWA@c...> wrote:

Are you emulating real switches or perfect instantaneous switches?

I have models for both ideal and real.

The reason is fairly simple, real switches do not turn on and off

instantaneously, if you have switches turn on while another turns

from on to off, the timing difference will cause the switches to

have

a short circuit for a brief period. By having less than 25% on

the

waveform you are insuring that the switches are all off before

turning one on, and thereby avoid that brief short.

If it were only that simple...



For example in the modeled QSD circuit that I am using, even if both

switches are on at the same time there is no "short circuit".



As a matter of fact, let's just forget about the other switch

and deal

with the case of ONE switch and ONE sample integrating capacitor.

This removes any discussion on switch turn on/off times causing

overlap/short circuits. For even this circuit the simulation

seems to

indicate that a 20-25% on time for the sampling clock is best.



This would translate to 20-25nS on time, 75-80nS off time ratio on a

100 nS period clock (10MHz).



Obviously this has something to do with the integration time of the

sampling capacitor and I am sure there is a mathematical equation

somewhere that predicts this. It is basically a sample and hold

circuit.


73 de Phil N8VB



P.S. LOL... I hope I know the difference between real and ideal

components after 26+ years in the field :-)














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