Thanks for posting the two images. If I understand the Si5351A clock generator, there could be two different cases.
In the case of no change in PLL frequency, only the Multisynth Divider would be used and the frequency change would be very fast. The datasheet advertises "Glitchless frequency changes" on page 1.
If the PLL frequency needed to be changed during a sweep, I believe the lock time could be close to a millisecond or longer. That would not be a problem but it would be noticeable with each data point requiring only a few milliseconds.
73, Kent
AA6P
