Hmmm, Interesting!
I can't open my old hieararchical sheets?
Might there be a bug, or is there a definitive no-no regarding backward
compatibility?
//Dan, M0DFI
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On Sunday 20 February 2011 23:28:26 you wrote:
Hello Charles.
Thank you.
have a look on this example :
<>
I fear, i did not understand this.
I named the labels of the Bus (2 wires, just for testing) Leit0 and
Leit1 (both ending with a Number) and lead them into the Bus. Then i
lead the Bus to a hierarchical Pin named Leit[0..1] (yes, two dots).
Outside the hierarchical schees, a placed this hierarchical pin (named
Leit[0..1]) to the subsheet, and lead a bus from this pin to the device,
were i again labeld the wires as Leit0 and Leit1.
But after creating the netlist, adding the footprints at CVpcb and
importing the netlist into PCBnew, i got only the footprints, but no
airwire.....
What is wrong?
I use BZR2754 RC 4A Ubuntu 10.10 with Debian Squeeze.
With best regards: Bernd Wiebus alias dl1eic
