开云体育

On Wed, 15 Apr 2020 at 17:47, Joe Monk <joemonk64@...> wrote:

> No doubt ... but MVCL/E are still millicode instructions. MVC is a hardware instruction.

Little is that simple these days...

> MOVE characters (MVC)
> – If <=16 bytes, it is cracked into separate load and store μops
> – If > 16 bytes, it is handled by a hardware sequencing logic inside the LSU
> – If the destination address is 1 byte higher than the source address
> (and they overlap), it is special cased into hardware as a 1-byte
> storage padding function (with faster handling)
> – If the destination address is 8 byte higher than the source address
> (and they overlap), it is special cased into hardware as a 8-byte
> storage padding function (with faster handling)
> – If other kinds of address overlaps, it will be forced into millicode
> to be handled a byte at a time

> MOVE LONG
? A special engine is built per CP chip for aligned copying or padding
functions at a page granularity
– The page-aligned copying or padding is done “near memory”, instead
of through caches, if
? Not executed inside a transaction
? Padding character specified is neither X’B1’ nor X’B8’
? A preceding NIAI instruction does not indicate that the storage data
will be used subsequently
? The operands must not have an access exception
? Length >= 4K bytes
? For moves: source and destination addresses are both 4K-byte aligned
? For padding: destination address is 4K-byte aligned
– Otherwise, the move process will operate through the caches (L1, L2…)
– Note that the evaluation is revised every unit-of-op
– For padding, even if starting address is not aligned, millicode pads
in cache to the first 4K-byte boundary, then uses “near
memory” pad engine for the next aligned 4K-byte pages until the
remaining length is less than 4K bytes. After that,
padding is done in cache again
? Near-Memory engine usage is best when the amount of data involved is
large and the target memory is not to be
immediately consumed in subsequent processes
– Since the special engine is shared within a CP chip, contention
among processors is possible
– Such contention is handled transparently by millicode and additional
delay may be observed



Tony H.