I copied the file from the wrong folder
John. The file I copied was an older file where the P channel FET
is wired incorrectly.
I changed the schematic so that 30 is the source (connected to
V+), 20 is the gate (connected to R6-U2 collector) and 10 remains
connected to the output. I replaced the old voltageMonitor.asc in
the groups.io 'file' section with the corrected file renamed
TestvoltageMonitor.asc.
The corrected file is posted in the groups.io 'file' section in
the same folder as before.
On 10/24/2024 3:51 PM, john23 wrote:
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Hello Terry,As you can see in thelink of the photo Pmos drain
is not creating a +12V pulse on the output.
The NMOS drain creates -12V very well
What could cause such a behavior in the PMOS drain?
LTspice portable folder is attached in the link below.
If its comfortable i could contact by E-mail also,to what E-mail
i should contact regarding a converstaion about this circuit?
Thanks.
