Are you considering designing an ASIC to communicate with the
parallel port of a PC?
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We are involved
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in BIDIRECTIONAL TRANSFER HERE.
Now we don't want to use centronics mode becoz it is unidirectional
only and we don't want ECP as it requires software compression and
commensurate decompression. So we r left with EPP.
Now let me repeat the question: whether I would require an ASIC to
control the protocol or should the FPGA take care of it??
thanx,
Aditya
