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after simulation, i do the following: e.g. on a resistor R1, holding alt button and hovering over the element R1 shows in the status bar "Left-click to plot R1 dissipation: ...". but doing so, does not add any plot. other than manually typing and adding the plot, is there a correct way for the same. or am i doing something wrong here? thanks.

Hi all, I'm working on a project that involves saturable transformer and when I try to model it in LTSpice, I can observe the saturation effects when there is sinusoidal voltage but I cannot really observe it when I supply pulsating DC voltage. Please find the LTSPICE files in here: /g/LTspice/files/Temp/SaturableTransformer.zip I went through all the information available on the internet and it helped me a lot. I am stuck with this since some time now. Can anyone please help me with it?

Looking for ideal fully differential amplifier spice model for XSPICE simulations. The one I have based on the XSPICE "gain" code model doesn't have any CMRR or care if outputs are swapped. Anything based on dependent sources would be good. * XSPICE Fully Differential OpAmp .subckt opamp inp inn outp outn in_offset=0 gain=300e3 out_offset=0 aint %vd(inp inn) %vd(outp outn) amp .model amp gain (in_offset='in_offset' gain='gain' out_offset='out_offset') .ends opamp The SE output OpAmp using the same structure works fine...

My file is AC_Coupling.asc and has text that has been made smaller than it was in older LTSpice versions. The weird part is some text is small but other text is normal. Using version 24.0.12.

I am still using version 24.0.11, and I am finding some problems with drawing a block diagram of a multi-stage circuit as a schematic. I know that LTspice isn't intended for that, but It's much simpler to use than some other drafting apps. The problems are: 1. I can't see the grid points. They have always been minute but now I can't see them at all. They used to be more visible on print-outs of schematics. 2. Drawing a wire with CTRL held down doesn't allow the wire to start and end off-grid. It's the same if I draw lines instead of wires. I can't find a 'Snap to grid' check box to untick. 3. Is there any way to change the dimensions of a rectangle after it is drawn? I guess not. Would it be better to use the symbol drafter? -- OOO - Own Opinions only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion Virus-free.www.avg.com

hello members, i was looking for a tool which can provide alternate diode models that match approximately to a given diode model. unfortunately, i could not find any website or software. it would great if anyone shares any information in this regard. thanking you in advance.

I am having issue with simulating experia BUK7S1R0-40H PET LTspice model characteristics https://www.nexperia.com/product/BUK7S1R0-40H when simulating mosfet with exact same setup as it is in application note i get quite different results for example output characteristic or transfer characterisitc. Anyone know what could be the problem here ?

Hello, I would like to use the LMR51606 in LTSpice. I only found an encrypted PSpice library on TI. I've already uploaded the file (LMR51606.zip). Unfortunately, I can't import the file into LTSpice. Is there a way to use the model, or does anyone have one? Thank you.

I have many testjigs that import digitised datasheet characteristic curves. An example of this would be: .subckt IB_400u 1 2 3 4 R1 3 4 1G B1 1 2 I=table(V(3,4) .inc BC848B_Ic_Vce_400u.inc +) This is used with a G-source called IB_400u, which in this case is the Ic vs. Vce characteristic of a transistor, i.e.: XG1 C 0 C 0 IB_400u The file BC848B_Ic_Vce_400u.inc is a simple table: +, 0, 0 +, 0.033713692946058194, 0.0037373737373737337 +, 0.07139456405596434, 0.007119195585620269 +, 0.09937242651150191, 0.01031229370884544 +, 0.11993258152246877, 0.014095645315621533 etc. This has always worked since LTspiceIV. With 24.1.4, it no longer works. Apparently, the new syntax checker works line by line, therefore the line: B1 1 2 I=table(V(3,4) ..will fail due to unbalanced parentheses. There seems to be no workaround that I have yet been able to figure, as the .inc directive must appear at the start of a line. I have uploaded example schematic to illustrate this issue: OP_Characteristic_rounding. This issue seems to be related to the previously reported issue with nested .STEP directives of the form: .step param A 0 10 1 + param B list 1 2 5 10 ..where the 2nd line is failing with 24.1.x. Example schematic uploaded: LTspice_24.1_Step_problem. -- Regards, Tony

Brady Ridgway uploaded some files to the Temp folder, which are now inside "Fuzz_Face_+G.zip". But Brady forgot to send a message here. Brady, please READ the group's guidelines on its main webpage. After uploading something, it is crucial that you compose and send an actual message here to this group, telling us what you did. You forgot to do that. Everyone else, here is the file Description that Brady used with his uploaded files: I am a beginner. I have uploaded two circuits, both of the classic Fuzz Face, which differ mainly in the power supply. Apart from the LT1054 and its components, the circuits are, I believe, identical. Graphing the voltage in most of the circuit produces very similar results, with the losses in the LT1054 being the cause. However, the current through the final capacitor C1/C3 (unfortunately I haven't indexed the circuits the same way) is completely different, as is the voltage at 'Vout'. Would someone please explain what I am missing? Some of us here will remember the Fuzz Face. It is a guitar "fuzz" circuit. If I remember correctly, it simulates poorly in LTspice, suggesting that the circuit works differently than SPICE simulations suggest. Andy

I have a python program kicking off LTspice as a background windows process with the following command. process = await asyncio.create_subprocess_exec(LTSPICE_PATH, "-b", "-run", solverFlag, fpath, stdout=asyncio.subprocess.PIPE, stderr=asyncio.subprocess.PIPE) I am running this process on a server and when I run it as my user account everything works as expected. Now I need to have it run as a windows service which requires a service account. I set this up and tried running but I get messages that symbols are missing from the simulation. I figured maybe the .ini file in the service account's folder was missing the symbol and library search paths so I made sure to match the .ini file in my service account's AppData/Roaming folder to match the one on my account. Unfortunately this did not help. Does anyone know why running in batch mode as a service account it would fail to look in the search paths?

Hello, I'm not sure whether this is the right place to ask about the difference seen in tube amplifier's transient analysis between LTspice and ngspice. The tube amplifier was the topic of this thread a few weeks ago. Let me know whether I can ask here.... Thanks, Carlo.

Is it possible to STEP 2 different MOSFETs in a simulation run. I've read about stepping models, and about basic subcircuits, but can you call one MOSFET file for the first step run and another MOSFET file for the second step run.

When I move the circuit graphs using mouse, it works fine, but when I move them using two fingers on the touchpad of my laptop, they shift the other direction (meaning when my fingers drift left, the graph moves right, vice versa). Not to mention i did not find a way to move the graphs up/down with touchpad too. Is there a way to modify the settings for this?

Hello, Lately, I needed to add an external piezoelectric buzzer to the internal ringer of my (bell) phone. I found, in the group’s archive, a circuit of Piezoelectric Buzzer, BuzFB.asc , made by analogspiceman - Aug 2012. Based on it, I made a model whose supply current is close to the one of a buzzer module I have. I added it, BuzzerModule.zip, to the group’s archive (though in the ’Temp folder’) as a subcircuit; BuzzerModule.asc + its symbol, BuzzerModule.asy (which is just a small box with 2 pins, IN+ and IN-). For instance, I built, for my ear, the low-voltage amplifier using TDA2822 (with a small electret micro and an NPN BJT pre-amp). Fortunately, it works as expected. Kerim

Hello All: WARNING: Less than two connections to node xlogic:u1:dp. This node is used by a:xlogic:u1:ddel. xlogic:u1 is a 74HC74 from the 74HC_v.lib of which my copy has the following header; * 74hc_v.lib * 74HCxxx Model libraray for LTSPICE from www.linear.com/software * Revision 0.55 08/20/2003 * Revision 0.56 08/21/2003 * Revision 0.57 02/04/2005 * Revision 0.58 03/28/2005 * Revision 0.59 03/29/2005 * Revision 0.60 07/09/2006 74HC191 added * Revision 0.61 10/16/2006 74HC4538 added * Revision 0.62 10/23/2009 74HC373 typo corrected * Revision 0.63 11/13/2009 74HC533 added * Revision 0.64 05/02/2010 74HC40103 added * Revision 0.65 30/05/2010 74HC244 added * Revision 0.66 01/30/2012 enabled B(VCC) in input/output driver models * Revision 0.67 10/04/2013 74HC_IN_0: V=LIMIT(0,V(in) -> V=LIMIT(0,V(in,VGND) * Revision 0.68 09/30/2014 corrected a typo HCT to HC in 74HC244 * Revision 0.69 02/01/2019 74HC05 added. The model is as follows; * D-filp-flop with asynchronous set and reset * CP->Q Tpd 47n/17n/14n * R/S->Q Tpd 52n/19n/15n * CP/R/S Tw 19n/7n/6n * D->CP Ts 6n/2n/2n * D->CP Th -6n/-2n/-2n * R,S Trem 3n/1n/1n .SUBCKT 74HC74 S C D R Q QN VCC VGND vcc1={vcc} speed1={speed} tripdt1={tripdt} .param td1=1e-9*(17-5-3-3)*4.0/({vcc1}-0.5)*{speed1} .param td2=1e-9*(19-5-3-3)*4.0/({vcc1}-0.5)*{speed1} .param td3=1e-9*(17+2-5-3-3)*4.0/({vcc1}-0.5)*{speed1} .param td4=1e-9*(5)*4.0/({vcc1}-0.5)*{speed1} * XIN1 S Si VCC VGND 74HC_IN_1 vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} XIN2 C Ci VCC VGND 74HC_IN_1 vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} XIN3 D Di VCC VGND 74HC_IN_1 vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} XIN4 R Ri VCC VGND 74HC_IN_1 vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} * ACDEL Ci 0 0 0 0 0 Cp 0 BUF tripdt={tripdt1} td={td1} ADDEL Di 0 0 0 0 0 Dp 0 BUF tripdt={tripdt1} td={td3} ARINV Ri 0 0 0 0 Rn 0 0 BUF tripdt={tripdt1} td={td2} ASINV Si 0 0 0 0 Sn 0 0 BUF tripdt={tripdt1} td={td2} A1 Di 0 Cp Sn Rn QNi Qi 0 DFLOP tripdt={tripdt1} td={td4} * XOUT1 Qi Q VCC VGND 74HC_OUT_1X vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} XOUT2 QNi QN VCC VGND 74HC_OUT_1X vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} .ends I was able to find the culprit, highlighted in red above. I was unable to devine where Dp should/could connect to eliminate the "Less than two connections" warning. If it has only one connection, then possibly Dp could be eliminated but, that escapes me also. I see that A1's data input is connected directly to Di which skips the ADDEL buffer. Should A1's data input be connected to Di (input pin) or should it be connected to Dp (buffered delayed output)? All for now

Hello all, I wanted to look through messages concerning the .FOUR command, but there are lots of messages containing the number 'four' which also get included, way too much so I gave up. Is there a way to exclude 'four' and search only for .FOUR (period-four)? Ryu

Hello , The analog devices website is not aloowing to filter OPAMPs exactly by the BW slew rate etc parmater. For example as you can see here.Its not allowing me to sort OPAMP models. Is there some catalog search engine you reccomend where I could sort OPAMPS by their properties? https://www.analog.com/en/product-category/high-voltage-op-amps-greaterthanequalto-12v.html#products-in-category Thanks.

Hello, In vain, I searched its model (TDA2822) in the group’s archive and on the internet. It is suitable for 32 Ohm headphone with an electret microphone and 2*1.5V battery. I have one ear working and its sensitivity has been degraded because of age. TDA2822 gain is fixed (39 dB = 89 V/V). In the bridge configuration (mono), its output voltage limit is doubled. Is there any chance to find its LTspice model? Thank you. Kerim

I currently have LTspice 17.1.14 installed on my Windows 10 computer. Can the latest version of LTspice 24 be installed without uninstalling LTspice 17? Thanks