74HC_V.lib Issue
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Hello All:
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WARNING: Less than two connections to node xlogic:u1:dp.? This node is used by a:xlogic:u1:ddel.
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xlogic:u1 is a 74HC74 from the 74HC_v.lib of which my copy has the following header;
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*? 74hc_v.lib
*? 74HCxxx Model libraray for LTSPICE from www.linear.com/software *? Revision 0.55 08/20/2003? ? *? Revision 0.56 08/21/2003??? ? *? Revision 0.57 02/04/2005 ? *? Revision 0.58 03/28/2005? ? *? Revision 0.59 03/29/2005? ? *? Revision 0.60 07/09/2006?? 74HC191 added? ? *? Revision 0.61 10/16/2006?? 74HC4538 added *? Revision 0.62 10/23/2009?? 74HC373 typo corrected *? Revision 0.63 11/13/2009?? 74HC533 added *? Revision 0.64 05/02/2010?? 74HC40103 added *? Revision 0.65 30/05/2010?? 74HC244 added *? Revision 0.66 01/30/2012?? enabled B(VCC) in input/output driver models *? Revision 0.67 10/04/2013?? 74HC_IN_0: V=LIMIT(0,V(in) -> V=LIMIT(0,V(in,VGND) ? *? Revision 0.68 09/30/2014?? corrected a typo HCT to HC in 74HC244 *? Revision 0.69 02/01/2019?? 74HC05 added. ?
The model is as follows;
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* D-filp-flop with asynchronous set and reset
* CP->Q Tpd 47n/17n/14n * R/S->Q Tpd 52n/19n/15n * CP/R/S Tw 19n/7n/6n * D->CP Ts 6n/2n/2n * D->CP Th -6n/-2n/-2n * R,S Trem 3n/1n/1n .SUBCKT 74HC74? S C D R Q QN? VCC VGND? vcc1={vcc} speed1={speed} tripdt1={tripdt} .param td1=1e-9*(17-5-3-3)*4.0/({vcc1}-0.5)*{speed1} .param td2=1e-9*(19-5-3-3)*4.0/({vcc1}-0.5)*{speed1} .param td3=1e-9*(17+2-5-3-3)*4.0/({vcc1}-0.5)*{speed1} .param td4=1e-9*(5)*4.0/({vcc1}-0.5)*{speed1} * XIN1? S Si? VCC VGND? 74HC_IN_1? vcc2={vcc1}? speed2={speed1}? tripdt2={tripdt1} XIN2? C Ci? VCC VGND? 74HC_IN_1? vcc2={vcc1}? speed2={speed1}? tripdt2={tripdt1} XIN3? D Di? VCC VGND? 74HC_IN_1? vcc2={vcc1}? speed2={speed1}? tripdt2={tripdt1} XIN4? R Ri? VCC VGND? 74HC_IN_1? vcc2={vcc1}? speed2={speed1}? tripdt2={tripdt1} * ACDEL? Ci 0 0? 0? 0?? 0?? Cp 0? BUF? tripdt={tripdt1}? td={td1} ADDEL? Di 0 0? 0? 0?? 0?? Dp 0? BUF? tripdt={tripdt1}? td={td3} ARINV? Ri 0 0? 0? 0?? Rn? 0? 0? BUF? tripdt={tripdt1}? td={td2} ASINV? Si 0 0? 0? 0?? Sn? 0? 0? BUF? tripdt={tripdt1}? td={td2} A1???? Di 0 Cp Sn Rn? QNi Qi 0? DFLOP? tripdt={tripdt1} td={td4} * XOUT1? Qi? Q?? VCC VGND? 74HC_OUT_1X? vcc2={vcc1} speed2={speed1}? tripdt2={tripdt1} XOUT2? QNi QN? VCC VGND? 74HC_OUT_1X? vcc2={vcc1} speed2={speed1}? tripdt2={tripdt1} .ends ?
I was able to find the culprit, highlighted in red above.
I was unable to devine where Dp should/could connect to eliminate the "Less than two connections" warning.
If it has only one connection, then possibly Dp could be eliminated but, that escapes me also.
I see that A1's data input is connected directly to Di which skips the ADDEL buffer.
Should A1's data input be connected to Di (input pin) or should it be connected to Dp (buffered delayed output)?
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All for now
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Hello eT,
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At first my confusion had me looking for a diode named "p".
Dp begins with D for diode but, now I realize that Dp is the output node of a BUF element as you have described.
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Removing the "ADDEL" BUF line eliminates the missing connection warning.
No need for the flip flop's data input to ride a BUF to nowhere.
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My realization of the 74HC74 has regularly been flip-flopping as expected without an "ADDEL" buffer so I commented it out to remove the warning.
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Thank you.
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All for now ?
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Sent:?Thursday, March 06, 2025 at 5:56 PM
From:?"eetech00 via groups.io" <eetech00@...> To:[email protected] Subject:?Re: [LTspice] 74HC_V.lib Issue Actually, in this case buf "ADDEL" output "DP" has a delay associated with it that isnt used.
It might have been intended for simulation of setup/hold time.
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It will take some testing.
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eewiz