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Hello All: WARNING: Less than two connections to node xlogic:u1:dp. This node is used by a:xlogic:u1:ddel. xlogic:u1 is a 74HC74 from the 74HC_v.lib of which my copy has the following header; * 74hc_v.lib * 74HCxxx Model libraray for LTSPICE from www.linear.com/software * Revision 0.55 08/20/2003 * Revision 0.56 08/21/2003 * Revision 0.57 02/04/2005 * Revision 0.58 03/28/2005 * Revision 0.59 03/29/2005 * Revision 0.60 07/09/2006 74HC191 added * Revision 0.61 10/16/2006 74HC4538 added * Revision 0.62 10/23/2009 74HC373 typo corrected * Revision 0.63 11/13/2009 74HC533 added * Revision 0.64 05/02/2010 74HC40103 added * Revision 0.65 30/05/2010 74HC244 added * Revision 0.66 01/30/2012 enabled B(VCC) in input/output driver models * Revision 0.67 10/04/2013 74HC_IN_0: V=LIMIT(0,V(in) -> V=LIMIT(0,V(in,VGND) * Revision 0.68 09/30/2014 corrected a typo HCT to HC in 74HC244 * Revision 0.69 02/01/2019 74HC05 added. The model is as follows; * D-filp-flop with asynchronous set and reset * CP->Q Tpd 47n/17n/14n * R/S->Q Tpd 52n/19n/15n * CP/R/S Tw 19n/7n/6n * D->CP Ts 6n/2n/2n * D->CP Th -6n/-2n/-2n * R,S Trem 3n/1n/1n .SUBCKT 74HC74 S C D R Q QN VCC VGND vcc1={vcc} speed1={speed} tripdt1={tripdt} .param td1=1e-9*(17-5-3-3)*4.0/({vcc1}-0.5)*{speed1} .param td2=1e-9*(19-5-3-3)*4.0/({vcc1}-0.5)*{speed1} .param td3=1e-9*(17+2-5-3-3)*4.0/({vcc1}-0.5)*{speed1} .param td4=1e-9*(5)*4.0/({vcc1}-0.5)*{speed1} * XIN1 S Si VCC VGND 74HC_IN_1 vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} XIN2 C Ci VCC VGND 74HC_IN_1 vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} XIN3 D Di VCC VGND 74HC_IN_1 vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} XIN4 R Ri VCC VGND 74HC_IN_1 vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} * ACDEL Ci 0 0 0 0 0 Cp 0 BUF tripdt={tripdt1} td={td1} ADDEL Di 0 0 0 0 0 Dp 0 BUF tripdt={tripdt1} td={td3} ARINV Ri 0 0 0 0 Rn 0 0 BUF tripdt={tripdt1} td={td2} ASINV Si 0 0 0 0 Sn 0 0 BUF tripdt={tripdt1} td={td2} A1 Di 0 Cp Sn Rn QNi Qi 0 DFLOP tripdt={tripdt1} td={td4} * XOUT1 Qi Q VCC VGND 74HC_OUT_1X vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} XOUT2 QNi QN VCC VGND 74HC_OUT_1X vcc2={vcc1} speed2={speed1} tripdt2={tripdt1} .ends I was able to find the culprit, highlighted in red above. I was unable to devine where Dp should/could connect to eliminate the "Less than two connections" warning. If it has only one connection, then possibly Dp could be eliminated but, that escapes me also. I see that A1's data input is connected directly to Di which skips the ADDEL buffer. Should A1's data input be connected to Di (input pin) or should it be connected to Dp (buffered delayed output)? All for now

Hello all, I wanted to look through messages concerning the .FOUR command, but there are lots of messages containing the number 'four' which also get included, way too much so I gave up. Is there a way to exclude 'four' and search only for .FOUR (period-four)? Ryu

Hello , The analog devices website is not aloowing to filter OPAMPs exactly by the BW slew rate etc parmater. For example as you can see here.Its not allowing me to sort OPAMP models. Is there some catalog search engine you reccomend where I could sort OPAMPS by their properties? https://www.analog.com/en/product-category/high-voltage-op-amps-greaterthanequalto-12v.html#products-in-category Thanks.

Hello, In vain, I searched its model (TDA2822) in the group’s archive and on the internet. It is suitable for 32 Ohm headphone with an electret microphone and 2*1.5V battery. I have one ear working and its sensitivity has been degraded because of age. TDA2822 gain is fixed (39 dB = 89 V/V). In the bridge configuration (mono), its output voltage limit is doubled. Is there any chance to find its LTspice model? Thank you. Kerim

I currently have LTspice 17.1.14 installed on my Windows 10 computer. Can the latest version of LTspice 24 be installed without uninstalling LTspice 17? Thanks

If I run a schematic with limit function in 24.0.12: b:u1:g_abmii22 u1:32b 0 i=v(u1:32)*(limit(((v(u1:31vdd1)-v(u1:vde))/(v(u1:31vdd1)-v(u1:31vdd2))), 0, 1)) If I run the same schematic with limit function in 24.1.4: u1:BG_ABMII22 u1:32B 0 I=v(u1:32)*if(((v(u1:31vdd1)-v(u1:vde))/(v(u1:31vdd1)-v(u1:31vdd2)))<0,0,if(((v(u1:31vdd1)-v(u1:vde))/(v(u1:31vdd1)-v(u1:31vdd2)))>1,1,(v(u1:31vdd1)-v(u1:vde))/(v(u1:31vdd1)-v(u1:31vdd2)))) Both simulations were run with expanded netlist turned on. I guess the expanded netlist format changed. But did the "Limit" function change too?

There appears to be a bug in LTspice Version 24.1 that is still present in V.24.1.4. The Repeat/EndRepeat directive in some PWL source directives throughs an error. See my uploaded example file PWL_Example1A.asc ERROR MESSAGE: net(3): Conflict: Last value differs from first value. V2 out2 0 PWL repeat for 3 (0 0 1m 5 2m 5 2.5m -1 3m -1 4m 2 4.5m 2) endrepeat ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Is it possible to transfer previous LTspice libraries from previous versions and add to newer LTspice versions? For instance, opamps and discrete active parts models, like transistors, that are available in version 4.23 is not available in version 24.0.12.

Trying to wrap my head around the new version 24 and yes, after no love at all in 24.1, I downgraded back to version 24.0.12. Lol! Anyway, I read that if I wanted to reliably and consistently use my own downloaded model files in circuits, I should create a library of my own to store them all. I already tidied up my workflow by keeping all my projects in a separate folder outside of LTSpice, with my models in subfolders (op-amps, transistors, diodes, etc..). Now I wanna go the extra step and start my own library of files so I don't have to use inc. statements every time. This is the correct path forward, no? It's been a while since I used LTSpice so, I may be completely wrong about all of this but, any help would be appreciated. I'm also looking for specific model files but, that will be another message. Thanks.

The option to save temp files in schematic directory has disappeared. The setting defaults to: Directory for temp files[*] C:\Users\(username)\AppData\Local\Temp If I clear the path (thinking it would default to the schematic directory), the default path is re-applied after clicking OK and reopening the settings I tried clearing the path, then entering a "*" (asterisk). I pressed enter and LTspice promptly killed itself. :-|

Hi, Does anyone have LTspice library file for BSC0403NSATMA1. This power mosfet by infineon is obsolete hence its LTspice library file is unavailable. I need it to model parasitics in dc dc converter.

If I add .inc/.lib statement on schematic: .inc file(3)_LT.txt It is converted to: .inc file(3)(overbar)LT.txt The "LT" characters get an overbar. Seems if a parenth, bracket, curly brace is preceded by an underscore, the followed text gets an overbar.

I had downloaded the MAX44241 Spice model and Ltspice schematic from Analog's website. For some reason I get the following error message. " Analysis: Time step too small; initial timepoint; trouble with u1: desd-instance d:u1:3 " I didn't change anything within the model or schematic itself so I'm not too sure why is occurred. Please note I am limited to use Ltspice XVII and can't update my software to LTspice 24, due to my company not approving that version of the software. I was wondering if there is a work around to get that error to not show up anymore and run without any issues within LTspice XVII. Link: MAX44241 Datasheet and Product Info | Analog Devices

is it possible to build a "Frequency dependent common mode inductor" in LTspice? f Ls Cs Rs [HZ] [uH] [pF] [ohm] 50 2040.3 4966800000 0.11861 100 2023.6 1251600000 0.13833 500 1997.3 50727000 0.47052 1000 1962.3 12905000 1.2977 5000 1636 619260 15.796 10000 1320.2 191850 36.245 50000 710.19 14266 144.23 100000 520.68 4864.9 247.12 500000 212.64 476.5 958.8 1000000 15.536 1631.6 1963.6 5000000 6.5795 154.02 79.92

Starting from the 12AU7 SUBCKT from http://www.duncanamps.com/spice/valves/dmtriodep.inc, I created a SUBCKT model for the 12AU7 heater, namely: *** 12AU7 Heater subckt model *** .SUBCKT 12AU7H H1 H2 +PARAMS: RCO=6.2 RHO=42 HTV=6.3 HWU=10.5 Rcool H1 HA {RCO} Rload HA HB 1M Esens HD 0 VALUE {V(HA,HB)*1000} Epwr HE 0 VALUE {V(H1,H2)*V(HD)/(PWR({HTV},2)/{RHO})} RH1 HE HF 91k CH1 HF 0 {HWU/1E6} EH2 HG 0 VALUE {V(HF)} RH2 HG HH 270k CH2 HH 0 {HWU/1E6} EH3 HJ 0 VALUE {LIMIT(V(HH)-0.75,0,1E6)*4} RH3 HJ HK 91k CH3 HK 0 {HWU/1E6} Ghot HB H2 VALUE {(1/(V(HG)+0.001))/({RHO}-{RCO})*V(HB,H2)} .ENDS I used it in a simple schematic doing a DC Sweep analysis on a DC current source connected to heater's pins H1 and H2 (one of the current source's pin is connected to GND). However Spice Error log reports the following: ERROR: Node U1:HB is floating and connected to current source G:U1:HOT Direct Newton iteration for .op point succeeded. What is the problem behind it ? Thanks. Carlo.

Right side of plot window is assigned to phase. Anyway to "hack" and assign right side of plot window to another parameter? Thanks.

Hello All, According to the help file: .MEAS TRAN res2 FIND V(out)*I(Vout) WHEN V(x)=3*V(y) Print the value of the expression V(out)*I(Vout) the first time the condition V(x)=3*V(y) is met. This will be labeled res2. When I put this on my schematc: .MEAS TRAN TooLow1 find V(XSW11:X1:Qc,XSW11:X1:Qe) when V(XSW11:X1:Qc,XSW11:X1:Qe)<1 The result is always: Measurement "toolow1" FAIL'ed So I ask myself, does "FAIL'ed" mean it failed to ever find V(XSW11:X1:Qc,XSW11:X1:Qe)<1 or does it mean that the .MEAS command has flawed syntax. So I tried it with V(XSW11:X1:Qc,XSW11:X1:Qe)<3 which happens all day long. V(XSW11:X1:Qc,XSW11:X1:Qe) goes to 2 volts regularly so the .MEAS command should find it <3 volts. But looking for <3 volts in a signal that regularly goes to 2 volts still produces: Measurement "toolow1" FAIL'ed. My syntax looks exactly like the help file's syntax. I don't see where I could be going wrong. Please help if you can. Thank You

I am new to LTspice and have been using version 24.0.12 for a few months. For learning, I have downloaded some schematics, like a CD4017Demo.asc as well as the CD4000_v.lib. Everything worked well in version 24.0.12 but crashes in version 24.1. I have ran into multiple erros that appear to be syntax issues or undefined variables in the CD4000_v.lib file. on Lines 90-92 of the CD4000_v.lib file, it has the following three param statements: .param td1=1e-9*(400-40-10)*5.0/(vdd1}*{speed1} .param td2=1e-9*(250-40-10)*5.0/(vdd1}*{speed1} .param td4=1e-9*(130-40-10)*5.0/(vdd1}*{speed1} LTspice 24.1 shows that the (vdd1} should be {vdd1} I used notepad and change the ( to a { and tried to rerun the simulation to the 24.1 version only to have more and more erros come up. Errors like Cval has not been defined, tripdt3 is undefined, speed4 is undefined. I have tried to read up on SPICE syntax and try to understand the various code in the CD4000_v.lib but at this point, I am not sure how to fix the .lib file so it will run in LTspice 24.1. any help is appreciated. John

Hello I am using python to run LTSpice simulations on a server (not currently using PyLTSpice). I am leveraging the cli to kick off asynchronous background tasks of LTSpice. The line of code looks like this, " process = await asyncio.create_subprocess_exec(LTSPICE_PATH, "-b", "-run", solverFlag, fpath, stdout=asyncio.subprocess.PIPE, stderr=asyncio.subprocess.PIPE)" I know LTSpice shows the percent completion of simulations in the GUI but is there a way I can get the progress of the simulation while it is running as a headless process? The best I can think of right now is to look at the size of the .raw file to make sure it is still growing so I may not have percent completion but at least I'd know the job simulation wasn't stalled for some reason. Your help appreciated!

Good morning, I have a question about symbols. Could a symbol be automatically generated from a (.lib) or (.sub) file??.. In this case it would be a comparator. If so, how could I generate it?