开云体育

Hallo,

I'm using scad3 for a few weeks and I'm very happy about the power
and speed of simulation. Now, I tried a more complex simualtion with
a LT1533 (I modified the sample) and got the following error:

Analysis: Timestep too small; time=0.000173642, timestep=1.25e-019:
trouble with node "n001"

What does that mean and how can I prevent this error. I tried to
modify the .tran command to use less steps, but this doesn't help.

Thanks, Rainer

Rainer,

I'm using scad3 for a few weeks and I'm very happy
about the power and speed of simulation. Now, I
tried a more complex simualtion with
a LT1533 (I modified the sample) and got the
following error:

Analysis: Timestep too small; time=0.000173642,
timestep=1.25e-019:
trouble with node "n001"
What does that mean and how can I prevent this
error.

It means the solver failed to converge for the
circuit. Usually you have to change some aspect
of the circuit to get it to run right. The
1533 is pretty complicated since it controls
the slew rate of switching via local feedback
loops. If you can't get it to run, you can
e-mail the circuit to the address on the
help=>about box for help with it. Note today
is a holiday in the USA.

I tried to modify the .tran command to
use less steps, but this doesn't help.

You can't tell it to use fewer timesteps.
It solves for a maximum timestep. You
can only stipulate a smaller one. You might
try the keyword "startup" on the .tran
command since it looks like your having
trouble with the intial conditions of your
simulation.

--Mike


__________________________________________________
Do you Yahoo!?
Yahoo! Shopping - Send Flowers for Valentine's Day

Mike,

thanks, for the quick answer!

I played a little around and I was able to complete simulate the
circuit. The wave-results are not as I wanted and I think I need a lot
more simulations until my circuit will work.

PM> can only stipulate a smaller one. You might
PM> try the keyword "startup" on the .tran
PM> command since it looks like your having
PM> trouble with the intial conditions of your
PM> simulation.
When I got another timestep error, LTspice ran a few time (3ms of
desired 10ms), until the error occurs. Are the data "in front of" the
error correct? Am I near some limits of the simulator, that causes the
problems of convergence? Are there some serial/parallel R/C/L I need
to take care about? Can I trust it?

Sorry for that elementary questions. I thought simulating a circuit is
easier... :-)

Gru, Rainer

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

Rainer,

I'm using scad3 for a few weeks and I'm very happy
about the power and speed of simulation. Now, I
tried a more complex simualtion with
a LT1533 (I modified the sample) and got the
following error:

Analysis: Timestep too small; time=0.000173642,
timestep=1.25e-019:
trouble with node "n001"
What does that mean and how can I prevent this
error.

It means the solver failed to converge for the
circuit. Usually you have to change some aspect
of the circuit to get it to run right. The
1533 is pretty complicated since it controls
the slew rate of switching via local feedback
loops. If you can't get it to run, you can
e-mail the circuit to the address on the
help=>about box for help with it. Note today
is a holiday in the USA.

Hello Mike,
Rainer could reduce the tolerances for the simulator in the Control
Panel -> SPICE box by a factor of 10 to 100.

Mike, could you tell us what tolerance is used in what type of
simulation?
I assume an .AC run doesn't use all of the tolerance settings used
in .TRAN simulation. I would try the settings below.
I am shure not all changes are useful.
Please give us a recommendation Mike.


Example:
--------

Abstol 1e-12 -> 1e-10
Reltol 1e-3 -> 1e-2
Chgtol 1e-14 -> 1e-12
TRtol 1
Voltol 1e-6 -> 1e-4
SStol 1e-3 -> 1e-2



Best Regards
Helmut

--- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote:

--- In LTspice@..., Panama Mike <panamatex@y...> wrote:

Rainer,

I'm using scad3 for a few weeks and I'm very happy
about the power and speed of simulation. Now, I
tried a more complex simualtion with
a LT1533 (I modified the sample) and got the
following error:

Analysis: Timestep too small; time=0.000173642,
timestep=1.25e-019:
trouble with node "n001"
What does that mean and how can I prevent this
error.

It means the solver failed to converge for the
circuit. Usually you have to change some aspect
of the circuit to get it to run right. The
1533 is pretty complicated since it controls
the slew rate of switching via local feedback
loops. If you can't get it to run, you can
e-mail the circuit to the address on the
help=>about box for help with it. Note today
is a holiday in the USA.

Hello Mike,
Rainer could reduce the tolerances for the simulator in the Control
Panel -> SPICE box by a factor of 10 to 100.

Mike, could you tell us what tolerance is used in what type of
simulation?
I assume an .AC run doesn't use all of the tolerance settings used
in .TRAN simulation. I would try the settings below.
I am shure not all changes are useful.
Please give us a recommendation Mike.


Example:
--------

Abstol 1e-12 -> 1e-10
Reltol 1e-3 -> 1e-2
Chgtol 1e-14 -> 1e-12
TRtol 1
Voltol 1e-6 -> 1e-4
SStol 1e-3 -> 1e-2



Best Regards
Helmut

Hello Gents,

Perhaps I can help here. Fixing convergence problems can be a complex
business but here is a sequence of things to try which has been found
useful by many Spice users. It applies to .TRAN convergence problems
which occur some way into the simulation rather than at the beginning.

The list is in order of usefulness and should be tried in this order.

1) Check your circuit! Correct any drafting errors and be sure that
there are no design errors.

2) Set RELTOL to .01 in the SPICE tab of the Control Panel (default
= .001).This trades off a little precision but speeds up the
simulation.

3) Set .OPTIONS ITL4=100 (default=10) This increases the number of
iterations at each time step before SPICE gives up.

4) Set ABSTOL to 1E-9 (default 1E-12) and VNTOL to 1E-3 (default 1E-
9). Both of these parameters are on the SPICE tab of the Control
Panel. They reduce the required precision slightly to make the
transient solution easier to find. The default values are intended
for use with IC designs. The vales suggested here are more
appropriate for power supply circuits.

5) Add realistic parasitics to your circuit. e.g. 3pF across diodes
and 5pF across BJT's. Add 100MEG to 1G resistors from each node to
ground. (Unfortunately LTSpice does not appear to have the
RSHUNT .OPTIONS parameter which would do this automatically).

6) Change the integration method to Gear (default is modified trap).
This parameter is also found on the SPICE tab of the Control Panel.
It should be used in conjunction with RELTOL = .01. Gear integration
tends to produce more stable if slightly less precise results than
trapezoidal integration. It is the preferred method for simulating
power circuitry as it performs better in situations where there is
ringing.


I hope this helps.

Russell

Helmut,

Mike, could you tell us what tolerance is used in
what type of simulation? I assume an .AC run
doesn't use all of the tolerance settings used in
.TRAN simulation. I would try the settings below.
I am shure not all changes are useful. Please
give us a recommendation Mike.

The tolerances that are typically most useful to
loosen are abstol, vntol, and chgtol. If you loosen
reltol, it's best not to loosed it too much. The
"No Bypass" check box is also often an important
nerve to try, especially if there are bipolar
transistors in the circuit.

Which tolerances are used by which analysis types:

.op .dc .tran .ac .noise
abstol yes yes yes no no
vntol yes yes yes no no
chgtol no no yes no no
reltol yes yes yes no no
trtol no no yes no no
sstol no no no no no

Note that .ac does not use any tolerances. It just
does linear(complex) math as accurate as double
precision allows. However, it's doing this on a
linearized version of the circuit from a .op and
the tolerances are used to find that solution for
non-linear circuits.

Sstol is steady state tolerance and is only used
to set how critical the steady state detector should
be. Usually this means how close the error amp
current must be to zero before be considered close
enough to zero. It's only used when the keyword
"steady" is on the .tran command and has no impact
on the accuracy of the simulation.

Trtol is sort of interesting because it does not
impact directly any accuracy but modifies the
strategy of the .tran integrator. This is typically
set to 7(it has no units) in other SPICE's. I set it
to 1 in LTspice because all those SMPS macro models
run better that way -- with no apparent simulation
artifacts for novice users. If you do transistor
level simulations, then it's probably better to
loosen trtol some.

--Mike


__________________________________________________
Do you Yahoo!?
Yahoo! Shopping - Send Flowers for Valentine's Day

--- In LTspice@..., "analogueman2002 <rd.weaver@n...>"
<rd.weaver@n...> wrote:

--- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote:

--- In LTspice@..., Panama Mike <panamatex@y...>

wrote:

Mike, could you tell us what tolerance is used in what type of
simulation?
I assume an .AC run doesn't use all of the tolerance settings

used

in .TRAN simulation. I would try the settings below.
I am shure not all changes are useful.
Please give us a recommendation Mike.

Hello Gents,

Perhaps I can help here. Fixing convergence problems can be a

complex

business but here is a sequence of things to try which has been

found

useful by many Spice users. It applies to .TRAN convergence

problems

which occur some way into the simulation rather than at the

beginning.

........

Hello Russell and Mike,
thanks for your advices to solve convergence problems.
I will keep your messages in my archive, because I am shure that
every SPICE user will run into these problems from time to time.

I recommend to spend a chapter about this in the help pages of
LTSpice.

Best Regards
Helmut