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Re: "Timestep too small" error while simulation


 

Helmut,

Mike, could you tell us what tolerance is used in
what type of simulation? I assume an .AC run
doesn't use all of the tolerance settings used in
.TRAN simulation. I would try the settings below.
I am shure not all changes are useful. Please
give us a recommendation Mike.
The tolerances that are typically most useful to
loosen are abstol, vntol, and chgtol. If you loosen
reltol, it's best not to loosed it too much. The
"No Bypass" check box is also often an important
nerve to try, especially if there are bipolar
transistors in the circuit.

Which tolerances are used by which analysis types:

.op .dc .tran .ac .noise
abstol yes yes yes no no
vntol yes yes yes no no
chgtol no no yes no no
reltol yes yes yes no no
trtol no no yes no no
sstol no no no no no

Note that .ac does not use any tolerances. It just
does linear(complex) math as accurate as double
precision allows. However, it's doing this on a
linearized version of the circuit from a .op and
the tolerances are used to find that solution for
non-linear circuits.

Sstol is steady state tolerance and is only used
to set how critical the steady state detector should
be. Usually this means how close the error amp
current must be to zero before be considered close
enough to zero. It's only used when the keyword
"steady" is on the .tran command and has no impact
on the accuracy of the simulation.

Trtol is sort of interesting because it does not
impact directly any accuracy but modifies the
strategy of the .tran integrator. This is typically
set to 7(it has no units) in other SPICE's. I set it
to 1 in LTspice because all those SMPS macro models
run better that way -- with no apparent simulation
artifacts for novice users. If you do transistor
level simulations, then it's probably better to
loosen trtol some.

--Mike


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