@Andy?

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See mosfets in weak inversion regions

Did I measure wrongly or had the wrong circuit connections compared to the circuit proposed in the IEEE paper ?

On Mon, May 12, 2025 at 12:33 AM, Cheng Fei Phung wrote:

Which transistors are incorrectly biased, if I may ask ?

The ones said to be in weak inversion zone so that they act as a very large resistor.? I do not know if it is a problem with biasing, or with sizes.

I did not change much the asc circuit file, I had been doing some study on the circuit operation details theory.

What changed, that makes it oscillate now?

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Andy

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On Mon, May 12, 2025 at 10:43 AM, Andy I wrote:

some transistors seem to be biased incorrectly as they do not behave according to your annotations

Which transistors are incorrectly biased, if I may ask ?

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I did not change much the asc circuit file, I had been doing some study on the circuit operation details theory.

On Sun, May 11, 2025 at 09:31 PM, Cheng Fei Phung wrote:

Attached is the ck_osc_transient_simulation_small_amplitude.zip

Just an FYI - it is not "attached".? It is "uploaded".? Nothing was attached to the message.

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That is the correct way to do it.? It was just stated wrongly.

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Andy

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Cheng Fei Phung,

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I apologize for not replying sooner.? I was taking a look at your original oscillator circuit (with the schematic borrowed from a paper at the ieeexplore.ieee.org website).? I do not believe that schematic is workable as an oscillator, when using the transistor models and sizes that you have provided.? I think the oscillator transistor lacks sufficient gain.? Also, some transistors seem to be biased incorrectly as they do not behave according to your annotations.? I was generating curves in LTspice to illustrate.? But alas, life got in the way for me and I was delayed.

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Have not yet seen your latest version.

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Andy

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What are your opinions on the?oscillation startup waveforms and stable phase simulation waveforms ?

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Note : The oscillation amplitude is a bit too small during stable phase, not sure how to fix it properly yet.

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Attached is the ck_osc_transient_simulation_small_amplitude.zip

@Andy

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> I rarely ever see cases where a crystal needs to be modeled in SPICE as more than two resonant circuits (series and parallel), and one is usually sufficient.

In this case, shall I use the or ?

On Sun, May 4, 2025 at 10:46 AM, Cheng Fei Phung wrote:

May I ask how to resolve the issue for floating node N004 ?

You might not need to, since LTspice resolves that problem for you, by connecting a 1T resistor (GFLOAT) from that net to ground.? Note that the message is a Warning, not an Error, and it fixes it and proceeds with the simulation.

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If 1 Tohms is not big enough, you can change the value of GFLOAT (.options GFLOAT=1e-15).? This resistor adds damping and reduces the Q of your crystal's equivalent circuit.? It might be insignificant in this case, but that might not always be true.? Also there are cases where adding a single resistor disturbs the balance of a balanced circuit - so it might (sometimes) be better to fix this problem yourself (instead of letting LTspice), by adding appropriate resistor(s), so that every circuit node has at least one DC path to ground.

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If you want to fix the problem yourself, add a very big resistor from the node to ground, or to another voltage if there is one that is better than ground.

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In your circuit, nodes Q1, N004, and N005 all lack a DC path to ground.? They have a DC path to each other.? They are isolated from ground by C1, C6, C7, and C8 on one end, and by C3 on the other end.

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LTspice picks one of those three nets (not quite arbitrarily) and adds GFLOAT between that net and ground, which fixes the problem for all of them because they share a DC path to each other.

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Note: The series RLC circuit or Figure 2(b) is an equivalent model of Figure 2(a) inside the IEEE paper.

Perhaps.? But neither is equivalent to the crystal model in Figure 1 in the paper.

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I rarely ever see cases where a crystal needs to be modeled in SPICE as more than two resonant circuits (series and parallel), and one is usually sufficient.? I wonder if the model in Figure 1 was supposed to represent the first three harmonics?? If that is the case, one might be able to omit the other harmonics.? Crystal oscillators can be tricky and under the right circumstances they can oscillate on an unintended harmonic.? Good oscillator circuits are designed to suppress the other harmonics.

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Andy

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@Andy

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I have done the three modifications as per your valuable advices.

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May I ask how to resolve the issue for floating node N004 ?

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Note: V004 is between Q1 and the R1 of the series RLC circuit.

Note: The series RLC circuit or Figure 2(b) is an equivalent model of Figure 2(a) inside the IEEE paper.

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Please advise, thanks !!

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On Sat, May 3, 2025 at 12:38 PM, Cheng Fei Phung wrote:

> Just be aware that all of your MOSFETs default to AS=0, AD=0, PS=0, and PD=0

Noted, is it safe to use 0 for these in your expert opinion ?

"Safe"?? I don't know, it depends on one's definition of "safe".

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Accurate?? Probably not.? Any time you omit something that you know about, or change a value from what it ought to be, it degrades accuracy.? If I remember right, SPICE MOSFET models include the capacitances of the bottom and sidewalls of the source and drain diffusions.? Leaving them set to 0 removes (ignores) that capacitance.? It might also ignore DC effects from their junction diodes.? Those omissions might be significant or insignificant.

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You might have noticed several warnings about PS and PD in your SPICE Error Logs.

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It is a simple (but tedious) schematic change to switch to the .SUBCKT models which automatically calculate AS, AD, PS, and PD.? Change the Prefix attribute to "X" to use the .SUBCKT version.

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Apparently these models were designed for a fab process with an effective length of 1.1 microns for each Source and Drain diffusion.? Hopefully that is correct.

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Andy

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@Andy

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Your advices are valuable and very useful !!! ? Thanks !!!

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> .MODEL statements are meant to use the pin-order D-G-S-B

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On Sat, May 3, 2025 at 05:45 AM, Cheng Fei Phung wrote:

See ck_osc_positive_supply.asc ,

That is a huge change!

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The fact that you moved the ground is insignificant.? It just shifts the voltages.? But you are no longer powering the "VN" net with a voltage source that had the polarity wrong, and that is a significant change.

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Not having studied the IEEE article, I wasn't sure but I suspected that the purpose of the "Output voltage regulator" section (and your M32) was to derive a regulated DC voltage on node VN.? And it looks like that is finally working now, in this schematic.? The earlier schematics you uploaded had that wrong, both by driving VN with a separate voltage source and by giving it the wrong polarity.

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However, I would not expect much difference in circuit performance at this stage.? The oscillator is the part of the circuit way over on the left, and everything else in the schematic is superfluous, except for the DC biasing voltages on nodes "g_a" and "g_b".? The output amplifier is just an output buffer and you could have omitted it because it is not part of the oscillator.? It adds a little load on the "Q1" net but I think that could be mostly ignored.

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What do you hope to achieve by sweeping the supply voltage, V_1?? Does it give you any significant information about the operation of the circuit?? In the end it does, after everything is working.? It tells you about things like supply voltage "pull".? But until the circuit oscillates, I think sweeping V_1 does not give you any useful information.

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I think I might be more interested in sweeping the DC voltage at the input of the oscillator's amplifier (node "M1_gate") and examining what is the transfer function and signal gain of M1.? That gain is what makes the oscillator oscillate - or perhaps why it does not oscillate.? Perhaps you should be looking there.

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I am now interpreting the underlying theory, I will get back to you next week with details.

That's good - but why have you not considered much of the advice you were given?? It seems to me that you are not very interested in trying to get your circuit right.? Do I read that incorrectly?

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Andy

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@Tony

See ck_osc_positive_supply.asc , I had actually checked the operating points conditions for each transistors according to circuit requirements.

I am now interpreting the underlying theory, I will get back to you next week with details.

You (Cheng Fei Phung) seem to be grasping at straws with pretty minimal understanding. In your situation, I would disconnect the "crystal" and feed a small transient 1.1MHz signal (say a hundred mV ppk or less) through a small capacitor (few 10s of pF). Verify that the amplifier has the expected operating point and has some actual gain at that frequency. Use a reasonable maximum time step (less than 50ns) and let the simulation run more than a few cycles (10 uS or longer). ?

On Fri, May 2, 2025 at 09:02 PM, Cheng Fei Phung wrote:

/g/LTspice/photo/302220/3911798?p=Created%2C%2C%2C20%2C2%2C0%2C0

still do not show any oscillatory phenomenon after adding RLC between Q1 and Q2.

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See?ck_osc.asc for the latest asc file

I see you added a simple RLC series resonant circuit to represent a crystal.? Do you know that it is an appropriate model?? Does this oscillator circuit depend on series resonance, or parallel?? (I don't know; I am just asking.)? Are the electrical characteristics OK to model the motional parameters of the crystal?

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Glancing at the IEEE article, it looks like they used a much more complex electrical model for the crystal, with not one or two but three series resonant RLC circuits in parallel with each other, plus three additional capacitors.? Your equivalent circuit is much simpler.? Is the simpler model adequate?

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The .tran statement on your schematic is ".tran 0 10 0 100u startup", so it calls for a Maximum Timestep of 100 us.? With a timestep of 100 us, it can simulate signals with frequencies up to about 5 kHz.? But your crystal model's series resonance is around 1.1 MHz.? To simulate a circuit oscillating at 1.1 MHz requires a timiestep that is smaller than 500 ns.? There is a chance that you made the Maximum Timestep so large that LTspice is incapable of seeing any sort of oscillation around 1 MHz.

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This is where simulations can become very difficult.? With a timestep smaller than 500 ns, it can take a very long time to simulate 10 seconds or 1000 seconds.

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Your N channel transistors are still upside-down, and the Bulk pins of many of the transistors are likely connected wrongly.? Also you have zero values for PS, PD, AS, and AD, which is technically incorrect, but I don't know how much difference it makes.? As you probably know already, I1 should not be there, but LTspice removes it.

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I suspect that your DC voltages are not right.? The negative supply voltage for the first three stages (node V1) is at -1.5 V which might be right.? But the regulated voltage for the output amplifier (node VN) is +1.5 V.? Is that right?? I think it powers the output amplifier with the wrong polarity.? Are you powering that section correctly?

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There is no DC path from node Q1 to ground, which extends to nodes N004 and N005.? LTspice tells you that the nodes float, and it "corrects" for it by adding GFLOAT to one of the nodes.? I think this won't affect the performance of this circuit, but I'm not sure.? GFLOAT will lower the Q of the resonant circuit a little.

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Note I have not read the IEEE article.

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Andy

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@Andy

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still do not show any oscillatory phenomenon after adding RLC between Q1 and Q2.

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See?ck_osc.asc for the latest asc file

I do not see a crystal on the schematic photo you uploaded (/g/LTspice/photo/302220/3911530).

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I wonder if that schematic is supposed to be just the on-chip part of a circuit, where you are supposed to connect a crystal externally, perhaps to the "Q1" and "Q2" pins.? But I think you have not done that.? Without a crystal connected, it might never oscillate.

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The other two screenshots you uploaded show somewhat small time scales.? You may need to start with simulations lasting hundreds of seconds or more, until you get something to happen.? In one of the photos, a voltage or a current is still changing even at 10 seconds, so clearly the circuit has not stabilized yet.? This does not mean that it will start oscillating if allowed to run longer, but it is possible.? If waveforms are still changing up to the end of your simulation, you have not waited long enough.

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In this case, I suspect that "waiting long enough" will not fix it.? I suspect the missing crystal is a critical deficiency.

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Andy

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On Fri, May 2, 2025 at 12:59 PM, Cheng Fei Phung wrote:

The upside-down issue is due to how mosfet_018.lib had been defined, please note that both PM and NM from this lib file had been verified previously.

See also /g/LTspice/photo/302220/3911530

In that photograph, which is a picture of a schematic drawn in a different program (not LTspice), it shows that the N-channel Source pins are lower down on the page.? ?That differs from how you drew them in LTspice.? In your schematic, the N-channel MOSFET Source pins are higher up.? They are indeed backwards (upside-down) compared to the schematic you tried to replicate.

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In LTspice's version of the MOSFET symbol, the Source pin is the one horizontally adjacent to the Gate pin, for both N and P channel types.

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With LTspice's version of the MOSFET symbols, one normally needs to rotate the P-channel symbols to make its Source pin higher up on the schematic - assuming that your schematic has the positive supply voltage up and the negative supply voltage down.? But the N-channel symbols should not be rotated.? They are already oriented correctly.

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It is unfortunate that there are multiple "standards" for MOSFET symbols.

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Andy

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