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Current Step Algorithm
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Hi...
I'm trying to get a behavioral current source algorithm to increase or decrease the amount of current every 1ms based on a window comparator.? I have a couple D-FF's with 0 prop delay and it's working, but the simulation is SLOW about 10 minutes for 500ms simulation.... I'm trying to speed it up a bit. Right now I have: I=if(v(rise_edge)==1,if(v(count_up)==1,I(B3)+0.5,if(v(count_down)==1,I(B3)-0.5,I(B3))),I(B3)) where V(rise_edge) is a D-FF rising edge detector with 0 prop delay and 0 rise time. V(count_up) and V(count_down) is the output of a window comparator that is typically sent to a FPGA and the FPGA increases or decreases the current. I(B3) is the behavioral current source Any other bright ideas on how to sense the rising edge and count up or down only once on the rising edge of the clock (or every 1ms of simulation?) JH |
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ehydra
I don't think I have the whole overview what do you want!
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I hopefully don't be killed by bullets from Mike... Here this circuits counts up three-times and then down twice controlled by input CLK and DIR and the dynamic count status is a single voltage output: You can now modify my idea in musings... A DFF without td is a bad idea. Sometimes it didn't work. I have no clue what is the reason. If you don't need exact voltage/current steps you can use idt(). Have fun! - Henry tindelsurf@... [LTspice] schrieb: Hi... |
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Henry,
I was able to figure it out with your help... and got my simulation time down to ~4.25 minutes, a great improvement... but now I at least know that the count table isn't what is slowing me down significantly.? I just have a complex loop.? And as Helmut pointed out... I knew the DFF solution wasn't very stable. One final question: is there a good way to speed up the transitions of the Sample and Holds?? I tried using td/trise/tfall, but it didn't appear to effect anything. Thanks for giving me the hint on the max/min counts too... that helped a lot!? I couldn't find anything in the help files about that! Love this place - you guys always get me pointed the right direction. Just FYI - if anyone ever reads this again (the yahoo search sucks, so I doubt it)... I was able to make Henry's suggestion a window comparator by setting Vdir to be centered about 0 and making the following statement for B1: V=if(V(dir)<-0.05,-1,if(V(dir)>0.05,1,0)).? I also speed up the clock to 1k to get my 1ms count increments. JH |
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ehydra
Hi JH -
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Sorry, I can't help you because it looks to complicated what you have done. Maybe it helps if you post the whole circuit. Even then the result thru help is not a whole faster reconfiguration but with new parameter settings. tripdt etc. It is maybe faster to not use compares but formulate all as float-operations: mul, div. max/min is not in the help-file because the whole counter circuit is a hack and surely not very liked by Mike. - H. tindelsurf@... [LTspice] schrieb: Henry, |
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> It is maybe faster to not use compares but formulate all as > float-operations: mul, div. That's not entirely true: multiplications and divisions are much slower compared to conditional checks, which may be the fastest, computational-wise. Still, I'll stick to what I said related to not using behavioural sources but, instead, E or G sources within a subcircuit. As they say, "your mileage may vary". Vlad ______________________ -- holding, among others: a universal analog/digital filter, block-level models for power electronics (and not only), math blocks with a more stream-lined approach, some digital ADC, DAC, (synchronous-)counter, JKflop, etc. |
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