Hi...
I'm trying to get a behavioral current source algorithm to increase or decrease the amount of current every 1ms based on a window comparator.? I have a couple D-FF's with 0 prop delay and it's working, but the simulation is SLOW about 10 minutes for 500ms simulation.... I'm trying to speed it up a bit.
Right now I have:
I=if(v(rise_edge)==1,if(v(count_up)==1,I(B3)+0.5,if(v(count_down)==1,I(B3)-0.5,I(B3))),I(B3))
where
V(rise_edge) is a D-FF rising edge detector with 0 prop delay and 0 rise time.
V(count_up) and V(count_down) is the output of a window comparator that is typically sent to a FPGA and the FPGA increases or decreases the current.
I(B3) is the behavioral current source
Any other bright ideas on how to sense the rising edge and count up or down only once on the rising edge of the clock (or every 1ms of simulation?)
Thanks,
JH
