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I wrote:

I think you misunderstood. The macro-model contains FAKE elements
that stand in for whole sections of transistors and stuff.

rainbowsally replied:

Understood. But they can be recreated using discretes. This truly
isn't a problem.

I hope I am neither offending, nor coming off sounding like a jerk ...
but I am still not sure you understand.

Let's say someone hands you a SPICE model for an IC, part number XYZ,
which you want to use in your circuit, and simulate in LTspice.

But being the curious type, you need to know what is in that model.
You want to see it visually in schematic form. So you spring for that
$100K conversion program which converts it into a schematic. And,
voila, it spits out a schematic consisting of:
a couple of voltage sources,
a few resistors and capacitors,
and a behavioral controlled source described by an equation.
Not a transistor in sight! In other words, it is one of those dreaded
"macro-models" that represents the behavior (rather than the
structure) of the XYZ part.

Sure, you could replace it or recreate it using discretes ... if you
knew what discretes to use! But you don't. All you have is the
macro-model. You know nothing else about the insides of this XYZ
part.

For that TLC555 that started this discussion, if the SPICE model you
have is one of these macro-models, then you might have no way to
understand why the input current is the same as it was for an old
NE555, even though the TLC555 is supposed to be a CMOS part.

Furthermore, it truly is a problem when the macro-model does not
accurately represent a certain behavior of the device that matters to
you. And that can easily happen.

Andy

Hi Andy-san!

Thanks your clear email.

How do you believe that it is blocked?

---> Blocked means bellow meanings.
1) The system blocked positively by any reason.
2) My profile information was modified by any reason which include my
operation.
-------------------------------------------------------------------------------------------------
This is my intuition which judged the surrounding situation synthetically.
------------------------------------------------------------------------------------------------

I have already tryed the Yahoo ID asuming as mr.shigematsu@... and
mr.shigematsu.
But I could not access the File of LTspice.

Q1) Would you tell me the method of ascertain the yahoo ID.

I have tried it according to their instruction, I could not modify
it.(failure).
So I have already asked to Yahoo about modifing my profile(Yahoo ID and my
name).
But I have not get the answer from them at present.

Shiggy



2012/8/30 Andy <Andrew.Ingraham@...>

**


Hi Shiggy-san,


You wrote:

My old email address (mr.shigematsu@...) is blocked in yahoo

system,

I think.
But I do not know the method of unblock.

How do you believe that it is blocked?

Yahoo has many components, including Yahoo email, Yahoo groups (like
this one), and others. My Gmail email address is not related to
Yahoo. I do not use that email address to access or download the
[LTspice] files. It seems like you were trying to use your email
address to try to download the [LTspice] files, but I don't understand
why you would do that.

But there is a Username (Yahoo calls it a "Yahoo! ID") that you need
to use when you sign in to Yahoo, which you must do before you can see
and download the [LTspice] files. You can only use a Yahoo! ID to
sign in to Yahoo. You cannot use a Gmail username to login to Yahoo
(and you can't use a Yahoo! ID to login to Gmail).

The Yahoo! ID is usually just a name. Yours might be "mr1.shigematsu"
... but Yahoo also lets you type it as "mr1.shigematsu@...".
They are not really asking for your email address when you sign in;
they are looking for your Yahoo! ID.

Andy

Ok, I see where I have to get to next.

Thank you.

RobertTalty wrote:

:-)

Looks like I'll be creating and studying asy files and libs for a while.

Jim Thompson wrote:

I wish there was. I understand Cadence claims to have such a tool...
sets you back ~$100K>:-o

So, if you want to see, you have to grunt>:-}

On the other side of the argument, though, sometimes you don't care
to see the innards. I regularly import a customer's portion of a
chip into my design, simply by connecting their netlist up as a
subcircuit. Thus I can simulate the whole enchilada proving my additions.

- Jim Thompson

That's a bit advanced for me, but I'd like to get to the point where I can do that too.

Thank you! :-)

Andy wrote:
<snip>

Nope. Not a problem. Those can be replaced by actual transistors once
the connections are identified.

I think you misunderstood. The macro-model contains FAKE elements
that stand in for whole sections of transistors and stuff.

Understood. But they can be recreated using discretes. This truly isn't a problem.

<snip>

And making use of these macro-models, can create problems (these are
the "problems" I alluded to before). A simple VCVS used as a
macro-model does not clip. A real op-amp does.

Precisely. :-)

But there aren't many models or even internal schematics on the internet. So I thought I'd start... and after I did one xx339 comparator with some degree of success (from an image of the schematic).

Someone around here did the entire NE555 chip and that has been extremely useful to me. I'd like to do the same with a few opamps and stuff.

And no... not going to search old message in this forum. Yow!

Well then you are missing out on a TON of useful information! This
group has a decade's worth of experience in them thar' archives.

I'm not a very good reader. I can parse a schematic MUCH better than I can parse words, but if you give me some realistic search terms, I'd give it a whirl.

I don't think I'd want to wade through all the results for "subcircuit", for example because as you say, in "ten years" most of the hits are going to be non-useful and I have dialup which is prohibitively slow for this kind of thing even using Ctrl-F to locate possible hits.

But never mind, Andy.

I'll figure it out myself eventually. I was just hoping there was an easier way.

If your approach is to say, "Give me the answers now, I don't want to
see the answer to the same question you wrote last (week, year,
whatever)", then I'm not so sure I'd want to help. Hopefully you will
reconsider.

Currently spending all "searching" time using datasheetcatalogs.com to find data sheets and manufacturers that I like and mouser.com to look up the same parts to get pricing. Took several hours to find some good prospects for the power output stage for kevin's amp (4th hack with realistic parts).

I don't have time.

But I'm willing to share the methods and results with everyone here. Hope that's not a problem. ;-)

Do you ever use the Internet? Google? Wikipedia? So if you are
willing to find an answer to something on the Internet that was
written two years ago, why won't you do the same here in this forum?

Good luck with your project.

It's not my project. It's Kevin's. And it's Gandolf's. And it's going to blow the doors off and come in at 1/4th the price of a cookbook solution.

--- In LTspice@..., rainbowsally <rainbowsally@...> wrote:

I love the scematics (especially analogspiceman's.. :-) they are
beautiful. I can even read my own!

But I'd like to literally see how some of these subcircuits are modeled
so I can see why things behave as they do. For example I got TLC555
which I believe is a CMOS 555 timer (and they're cheap and giving 'em
away right now), but when I measure the input currents they are
identical to the old NE555 model we have in our lib folders somewhere.

So what I'm asking is this. How do I get a visual representation of the
components MINUS the *.asy file. And I don't care how many steps it
might take. Might even write a converter program if there isn't a way
to do this inside ltspice.

Drawing them component by component is on my don't-do list.

:-)

Over MANY years I've tried lots of netlist to Schematic conversion programs. To be honest none of them work well for Analog circuits.

For digital schematics the best I ever saw was from a company called Veiwlogic, but this company has long since faded from the scene. Many professional IC design packages include netlist to Schematic conversion because it is sometimes needed when you are debugging digital Logic that was auto generated from Verilog code.

Unfortunately the tool you are searching for does not exist, so save yourself time searching and learn to read Spice netlists and draw the schematic by hand, then reenter it into LTspice and compare the schematic's netlist with the original netlist. There are automatic tools for comparing netlists, typically I'd use the Layout Vs Schematic (LVS) comparison tool BUT enter two netlists instead of a Layout and schematic.

-Robert

Your are right, but i am looking toward extracting the results from a text
file which is directly obtained by executing scad3.exe from the command
window! I mean, I want to bypass the waveform window!

The netlist for a subcircuit is essentially a "directed graph" (not a Cartesian graph, nor radial graph like you drew in high school) See the "tutorial/GraphDrawing" in the Mathematica help.

Mathematica has plotting tools for "graphs" and "directed graphs". Any edge and any vertex can be given a name. Beyond that, Mathematica has built in the ability to use any Mathematica object for a node label or edge label (or more generally for any legend entry, plot point, etc.) and such functionality can be nested arbitrarily deep.

There are 7 precanned "Methods" for organizing the drawing. None of these are likely to pretty like analogspiceman pretty, but if you got lucky, one of the methods might provide an aha! perspective. The most obvious problem is that a human wants to see functionally related nodes clumped together and the functional information is generally not available in the LTSpice netlist.

Using BFI, you could look at your first attempt, and decide that it would be smart to assign each connection to node zero in the LTSpice subcircuit netlist to a separate vertex in the output graph and use a little image of a ground symbol for each of those vertices. Similarly for each node YOU judge to be worthy of being given a netlist name as opposed to a netlist number.

To fully automate the process you'd probably want to use LISP or Prolog and plan on spending the rest of your life writing code to run on a cluster.

I wish there was. I understand Cadence claims to have such a tool... sets you back ~$100K >:-o

So, if you want to see, you have to grunt >:-}

On the other side of the argument, though, sometimes you don't care to see the innards. I regularly import a customer's portion of a chip into my design, simply by connecting their netlist up as a subcircuit. Thus I can simulate the whole enchilada proving my additions.

- Jim Thompson

I wrote:

It is NOT trivial to convert a netlist of one form or another, into a
human-readable schematic.

rainbowsally wrote:

Not talking about a netlist.... I don't think. (???)

There are all kinds of netlists. A netlist is generically just a file
that has all the information about connectivity of your circuit.

Most people who inquire about converting a SPICE model to a schematic,
are starting with a subcircuit, which IS a SPICE netlist. It is a
text file that lists all the components as well as how they are
interconnected. I thought that was what you were starting with.

By the way, the *.asy file is just the symbol you see on your
schematic. It itself has NONE of the information about the schematic
it represents.

Many IC models are macro-models and contain functional equivalents for
whole blocks of circuitry. Some IC macro-models don't even contain a
single transistor! And that can give rise to various problems.

Nope. Not a problem. Those can be replaced by actual transistors once
the connections are identified.

I think you misunderstood. The macro-model contains FAKE elements
that stand in for whole sections of transistors and stuff.

Say you've got an IC op-amp. Someone can replace the whole op-amp
with a VCVS, which is just an E-element in SPICE. Doing so loses all
of the components that made up that IC! You would not be able to come
along later and restore the actual transistors to the schematic,
unless you (somehow) also had a schematic in your other hand for the
insides of the IC op-amp that was used.

So I'm saying the SPICE model you have for (say) that TLC555 you have,
*might* not even have any transistors in it! It might be just a
functional equivalent of a generic '555. (Hopefully not!)

And making use of these macro-models, can create problems (these are
the "problems" I alluded to before). A simple VCVS used as a
macro-model does not clip. A real op-amp does.

And no... not going to search old message in this forum. Yow!

Well then you are missing out on a TON of useful information! This
group has a decade's worth of experience in them thar' archives.

If your approach is to say, "Give me the answers now, I don't want to
see the answer to the same question you wrote last (week, year,
whatever)", then I'm not so sure I'd want to help. Hopefully you will
reconsider.

Do you ever use the Internet? Google? Wikipedia? So if you are
willing to find an answer to something on the Internet that was
written two years ago, why won't you do the same here in this forum?

Good luck with your project.

Andy

BTW, that wasn't really the problem with the url I posted. When I joined the copied url from the actual file (which contains the user's id and isn't the real path) and the path to the files area, I accidentally left an extra '//' in the path.

I'll be more careful in the future.

Andy wrote:

For all who were E-Mailed off list I am sorry I did not realise till too late. That was my mistake and will stop.?
Best wishes and good luck at what you do. You all did help out a stupid electronic person thou.

[Non-text portions of this message have been removed]

Yeah. Us old hippies need to stick together. :-)

Absolutely the best of luck to you, Kevin. Email me offlist if there's anything you think I might be able to help with.

Kevin Byrne wrote:

Andy wrote:

So what I'm asking is this. How do I get a visual representation of the
components MINUS the *.asy file. And I don't care how many steps it
might take. Might even write a converter program if there isn't a way
to do this inside ltspice.

It is not done by LTspice. (LTspice needs no schematic representation
of what a circuit or subcircuit looks like ... the SPICE netlist has
everything it needs.)

Yes, but not everything *I* need.

It is NOT trivial to convert a netlist of one form or another, into a
human-readable schematic.

Not talking about a netlist.... I don't think. (???) Talking bout a literal *.asy file which should have all the info in it necessary to make some kind of representation of as a schematic -- even if it's an IC block with 100 pins all on one side. the sym file can be modified.

The question has been asked here a few times before. Some research
has been done, and some of the previous discussions touched on some of
that research and a few other programs that offer such capability.
Try searching through the group's archives for those earlier message
threads.

Ouch.

Many IC models are macro-models and contain functional equivalents for
whole blocks of circuitry. Some IC macro-models don't even contain a
single transistor! And that can give rise to various problems.

Nope. Not a problem. Those can be replaced by actual transistors once the connections are identified.

Depending on what you are looking for, a full schematic may not be
needed. It might be possible to trace out everything connected to the
input pin in question, and get a better handle on why it behaves the
way it does. Note: it may not be pretty what you discover about the
subcircuit; many subcircuits are poorly constructed and/or used
improperly!

Andy

(PS: I'll bet that some of us SPICE oldtimers got to be pretty good at
turning SPICE netlists into hand-drawn schematics, for those times
when we really needed to know what a circuit looks like.)

If I could see before/after shots of a couple of them I'd have something to start with. As it is, I'm just getting up to speed on the "heirarchy"

file.asc (top)
|-- file.asy (schematic)
`-- top.sub (external assembly of .model's)

Currently wobbly but ok with *.asy, and completely flummoxed by *.sub. which I'd like to be able to convert to/from.

Thanks for the reply Andy! :-)

And no... not going to search old message in this forum. Yow! Having enough probs identifying a small realistic set of good cheap transistors, especially for driver and power output for an audio amp.

The spaces prefixing the folder names are apparently a convenience for
posting aesthetically pleasing url paths to places in our files area.

Those spaces are intentionally there, in some of the folder
(directory) names, to group the important folders near the top of the
(alphabetical) listing, on the group's website.

I think that was Helmut's doing, but he is one of a few group
moderators so it might be one of the others too.

Andy

So what I'm asking is this. How do I get a visual representation of the
components MINUS the *.asy file. And I don't care how many steps it
might take. Might even write a converter program if there isn't a way
to do this inside ltspice.

It is not done by LTspice. (LTspice needs no schematic representation
of what a circuit or subcircuit looks like ... the SPICE netlist has
everything it needs.)

It is NOT trivial to convert a netlist of one form or another, into a
human-readable schematic.

The question has been asked here a few times before. Some research
has been done, and some of the previous discussions touched on some of
that research and a few other programs that offer such capability.
Try searching through the group's archives for those earlier message
threads.

Many IC models are macro-models and contain functional equivalents for
whole blocks of circuitry. Some IC macro-models don't even contain a
single transistor! And that can give rise to various problems.

Depending on what you are looking for, a full schematic may not be
needed. It might be possible to trace out everything connected to the
input pin in question, and get a better handle on why it behaves the
way it does. Note: it may not be pretty what you discover about the
subcircuit; many subcircuits are poorly constructed and/or used
improperly!

Andy

(PS: I'll bet that some of us SPICE oldtimers got to be pretty good at
turning SPICE netlists into hand-drawn schematics, for those times
when we really needed to know what a circuit looks like.)

I love the scematics (especially analogspiceman's.. :-) they are beautiful. I can even read my own!

But I'd like to literally see how some of these subcircuits are modeled so I can see why things behave as they do. For example I got TLC555 which I believe is a CMOS 555 timer (and they're cheap and giving 'em away right now), but when I measure the input currents they are identical to the old NE555 model we have in our lib folders somewhere.

So what I'm asking is this. How do I get a visual representation of the components MINUS the *.asy file. And I don't care how many steps it might take. Might even write a converter program if there isn't a way to do this inside ltspice.

Drawing them component by component is on my don't-do list.

:-)

For the record Helmut ?I am not a computer geek, electronic geek but I have been getting 100 to 300 E-mails?a day quite a few of the stupid kind. I do not know how to spot spam, hackers or any thing else. I do not reply like you said due to my understanding your words and respect for others. Please accept my apology for just being new, not a smart ass.
Not my style. I did receive a lot of help thou, and have a number of books on order and am a lot further along in my study's of audio equipment. I am a disabled Vet., a certified auto mechanic and know the value of study and asking questions. Best to you and advise as I am a person who listens and takes a beating and changes when I am wrong
Kevin

[Non-text portions of this message have been removed]

The "%" character is 'hexidecimal' for a <space> (0x20 or decimal 32) needed because spaces will terminate urls and urls can't be quoted like normal filesystem paths.

The spaces prefixing the folder names are apparently a convenience for posting aesthetically pleasing url paths to places in our files area.

Andy wrote:

--- In LTspice@..., "Majid" <rafei.majid@...> wrote:

Dear all,
Hi.
The question is "How can I calculate network parameters
in LTSpice so that the results will be readable from the
output .log or .saw (ascii type) files?"

Hello Majid,

After you have run the simulation, you can export the results.

Make waveform window the active window.

File -> Export

A dialog window will pop up. Choose the items you want to be
exported.

Best regards,
Helmut