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On 24/07/2013 21:16, sct5033 wrote:

Win 7 Enterprise (managed by my University)
SP1

LTspice was installed as administrator, then run as user. However I have tried to Run as Administrator with no difference.

I would install in something like "c:\ltspice" rather than the default folder, if it will let you....

--- In LTspice@..., John Woodgate <jmw@...> wrote:

In message <kspabh+oak6@...>, dated Wed, 24 Jul 2013, sct5033
<sct12@...> writes:

I have a new installation of LTspice on a Windows 7 OS.

Which flavour of Win 7 and which SP level? Are you running as
Administrator?
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Why is the stapler always empty just when you want it?

John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

--
Dave Wade G4UGM
Illegitimi Non Carborundum

Hello,

You have a mistake in one line.

E1 50 40 51 0 1 E2 40 39 52 0

It should be two lines.

E1 50 40 51 0 1
E2 40 39 52 0

Have you seen that it requires a symbol with this Netlist order
in the symbol?

* 1 INVERTING INPUT
* 2 NON-INVERTING INPUT
* 3 OUTPUT
* 4 POSITIVE POWER SUPPLY
* 5 NEGATIVE POWER SUPPLY

I made a general symbol xopamp_st2.asy ans I also made a
schematic example with this symbol and your subcircuit.

Files > Lib > MC33078_ST_test.zip



Best regards,
Helmut

In message <kspabh+oak6@...>, dated Wed, 24 Jul 2013, sct5033 <sct12@...> writes:

I have a new installation of LTspice on a Windows 7 OS.

Which flavour of Win 7 and which SP level? Are you running as Administrator?
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Why is the stapler always empty just when you want it?

John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

I have a new installation of LTspice on a Windows 7 OS. I am trying to run a hierarchical schematic from a network share, with all of the hierarchical files in the same directory. I can run this model from the network on a MacBook with Wine, and on a Win XP installation running on VMWare from the same Mac.

However the model will not run on the Win 7 workstation. The error is "Missing schematic(s) of the hierarchy" with the first level hierarchical filenames listed in all lower case characters. The actual files have names using mixed case. Wine and VMWare/Win XP can deal with the mixed case names, but the Win 7 installation cannot.

It is even a bit more weird. On the Win 7 machine, the schematic editor has no problem with this hierarchy. Double clicking on a hierarchical symbol brings up its lower level schematic. The hierarchy has several levels, and I can drill down to its lowest level. The problem is that, on Win 7, the hierarchy will not run.

I admit to being new to Win 7, but other programs run fine, and the fact that the schematic editor works as expected makes it all the more mysterious. I have spent some time looking through the message base, to no avail.

Has anyone seen a problem like this?

this not working (( out is a deadline

** Standard Linear Ics Macromodels, 1993.
** CONNECTIONS :
* 1 INVERTING INPUT
* 2 NON-INVERTING INPUT
* 3 OUTPUT
* 4 POSITIVE POWER SUPPLY
* 5 NEGATIVE POWER SUPPLY
.SUBCKT MC33078-ST 1 2 3 4 5
***
.MODEL MDTH D IS=1E-8 KF=2.286238E-16 CJO=10F

* INPUT STAGE

CIP 2 5 1.200000E-11
CIN 1 5 1.200000E-11
EIP 10 5 2 5 1
EIN 16 5 1 5 1
RIP 10 11 2.363636E+00
RIN 15 16 2.363636E+00
RIS 11 15 1.224040E+01
DIP 11 12 MDTH 400E-12
DIN 15 14 MDTH 400E-12
VOFP 12 13 DC 0
VOFN 13 14 DC 0
IPOL 13 5 1.100000E-04
CPS 11 15 2.35E-09
DINN 17 13 MDTH 400E-12
VIN 17 5 1.000000e+00
DINR 15 18 MDTH 400E-12
VIP 4 18 1.000000E+00
FCP 4 5 VOFP 1.718182E+01
FCN 5 4 VOFN 1.718182E+01
FIBP 2 5 VOFN 4.545455E-03
FIBN 5 1 VOFP 4.545455E-03

* AMPLIFYING STAGE

FIP 5 19 VOFP 9.545455E+02
FIN 5 19 VOFN 9.545455E+02
CC 19 29 1.500000E-08
HZTP 30 29 VOFP 1.523529E+02
HZTN 5 30 VOFN 1.523529E+02
DOPM 51 22 MDTH 400E-12
DONM 21 52 MDTH 400E-12
HOPM 22 28 VOUT 5.172414E+03
VIPM 28 4 1.500000E+02
HONM 21 27 VOUT 4.054054E+03
VINM 5 27 1.500000E+02
DBIDON1 19 53 MDTH 400E-12
V1 51 53 0.68
DBIDON2 54 19 MDTH 400E-12
V2 54 52 0.68
RG11 51 5 3.04E+05
RG12 51 4 3.04E+05
RG21 52 5 0.6072E+05
RG22 52 4 0.6072E+05
E1 50 40 51 0 1 E2 40 39 52 0 1
EDEC1 38 39 4 0 0.5
EDEC2 0 38 5 0 0.5
DOP 51 25 MDTH 400E-12
VOP 4 25 1.474575E+00
DON 24 52 MDTH 400E-12
VON 24 5 1.474575E+00
RAJUS 50 5 1E12
GCOMP 5 4 4 5 8.1566068E-04
RPM1 5 80 1E+06
RPM2 4 80 1E+06
GAVPH 5 82 50 80 3.26E-03
RAVPHGH 82 4 613
RAVPHGB 82 5 613
RAVPHDH 82 83 1000
RAVPHDB 82 84 1000
CAVPHH 4 83 0.159E-09
CAVPHB 5 84 0.159E-09
EOUT 26 23 82 5 1
VOUT 23 5 0
ROUT 26 3 4.780354E+01
COUT 3 5 1.000000E-12
.ENDS

where do you read about syntax command ltspice and pspice
best solution is a little program to conversion

--- In LTspice@..., "bordodynov" <BordodunovAlex@...> wrote:

Hi Heinz-W. Schockenbaum and Macy.I do not understand why I needed to
update fonts.

Sorry, you don't need to. No offence intended.
Your contributions are very good and appreachiated.
Your message itself is readable, but your name is "scrambled" or may be in cyrillic font.

I use firefox.

Maybe Macy is right and i need to install another character set for
""bordodynov" <BordodunovAlex@..." which nearely always looks scrambled - except your last messages.

Sorry

hws

Does anyone know of the whereabouts of a .LIB or .SUB file for Avago's HCPL-3323 Optocoupler? There is nothing on their web sits.

Dennis

Dear John:



I agree, very large values increase the likelihood of noise pickup,



Make even the smallest amount of circuit board contamination a real problem.





At the other extreme, very small values are difficult to measure even with



“four wire ohms” technique, and require us to consider things like a
“thermal voltages”.



High end bench/system millimeters have so called “offset compensation” but
even that is



not enough for very small values (0.001 Ohm and below) One time I measured
a



resistance near 1E-6 Ohms, but only with very modest accuracy. I was forced
to use



an external current source of about 500ma, and an external 6 ? digit
multimeter.



I essentially had a computer controlled ohmmeter, with computer controlled
relay contacts



(HP 3488 Switch/control unit) First I would use the software to turn on the
current source,



And measure the voltage drop across the cooper conductor, then I would turn
off the current source



(just open the relay contacts that are in series with the current source and
copper conductor) and take a



Second measurement. Take the second measurement and subtract from the first
(this is the same as “offset compensation” on your multmeter)



The rest is just ohm’s law.



















_____

From: LTspice@... [mailto:LTspice@...] On Behalf Of
John Woodgate
Sent: Wednesday, July 24, 2013 1:37 PM
To: LTspice@...
Subject: Re: [LTspice] Re: Article on EDN by Mike Robbins





In message <ksp2g0+dm2f@... <mailto:ksp2g0%2Bdm2f%40eGroups.com> >,
dated Wed, 24 Jul 2013, Helmut
<helmutsennewald@... <mailto:helmutsennewald%40yahoo.com> > writes:

I always recommend to stay away from nano-Ohm or micro-Ohm values of
resistance if possible.

In normal circuits, there is no need for Gohms, kH and kF either. Any
extreme value might cause an obscure problem.
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Why is the stapler always empty just when you want it?

John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK





[Non-text portions of this message have been removed]

I don't remember seeing the following difference between the regular
solver and the alternate solver being mentioned before.

"In fact, the Alternate Solver of LTspice has been doing
extended-precision circuit simulation for a long time."

This difference was extracted from one of the comments to the article.

Howard

In message <ksp2g0+dm2f@...>, dated Wed, 24 Jul 2013, Helmut <helmutsennewald@...> writes:

I always recommend to stay away from nano-Ohm or micro-Ohm values of resistance if possible.

In normal circuits, there is no need for Gohms, kH and kF either. Any extreme value might cause an obscure problem.
--
OOO - Own Opinions Only. With best wishes. See www.jmwa.demon.co.uk
Why is the stapler always empty just when you want it?

John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

--- In LTspice@..., "haubmi1" <Michael.Haub@...> wrote:

Hi,

in that article Mike Robins claims superiority of their "CircuitLab" simulator over all other simulators in respect of numerical resolution.



He shows a LTspice screen with a totaly off solution.

In fact this circuit needs the "alternate" solver to get the right solution.

Is there a secret .option for seting the solver?

Help says:
"There is no .option to specify which solver is used, the choice must be made before the netlist is parsed because the two solvers use different parsers."

Why not?
Wouldn't it be better than puting a text on the shematic, saying "attention: switch to alternate solver for this deck".

Greetings
Michael

Hello,

The Normal Solver has no problems, if the value of R1 is set
to a value of 100uOhm or higher.

I always recommend to stay away from nano-Ohm or micro-Ohm
values of resistance if possible.

If one only needs a current sense in SPICE, then a 0V V-source
is better then using a resistor.

Best regards,
Helmut

I think for the most part you answered your own questions.

Is there a secret .option for seting the solver?

Apparently not, as your next line stated:

Help says:
"There is no .option to specify which solver is used, the choice must be
made before the netlist is parsed because the two solvers use different
parsers."

Why not?

Because LTspice needs to parse (read and decode) the netlist in order to
find the .option. By then it is too late to change the parser.

Wouldn't it be better than puting a text on the shematic, saying
"attention: switch to alternate solver for this deck".

It might be nice, yes. But as the LTspice developer says, it can't be done.

I suppose you could suggest to Mike that he re-consider ... to make LTspice
start over from the beginning if it finds an .option to change the solver.

Regards,
Andy

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

--- In LTspice@..., "Helmut" <helmutsennewald@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

Hello Jason,

Please try my suggestion with cshunt as I mentioned before.

Best regards,
Helmut

Hello Helmut,

I did try that - 1e-12 and 10e-12 still no success

Hello Jason,
I never use higher cshunt values than 1e-15.

You could send me one of your designs if you can't upload it
for some reason. I would then try on it.

Best regards,
Helmut

--- In LTspice@..., "Helmut" <helmutsennewald@...> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

Hello Jason,

Please try my suggestion with cshunt as I mentioned before.

Best regards,
Helmut

Hello Helmut,

I did try that - 1e-12 and 10e-12 still no success

Sorry for confusion.

Alex, What YOU write comes through fine

hws, Update YOUR fonts.



--- BordodunovAlex@... wrote:

From: "bordodynov" <BordodunovAlex@...>
To: LTspice@...
Subject: [LTspice] Re: Step Change to k of Coupled Inductors During Transient Analysis
Date: Wed, 24 Jul 2013 05:51:43 -0000

Hi Heinz-W. Schockenbaum and Macy.I do not understand why I needed to
update fonts. I use the browsers Mozilla FireFox and Google Chrome. I
looked at her letters with them. Everything is fine. These browsers I
reinstalled in May. I will make an attempt to change the font of the
letter.Bordodynov.
--- In LTspice@..., Macy wrote:

it's readable for me.

update your browser's font

--- schockenbaum@... wrote:

From: "Heinz-W. Schockenbaum" schockenbaum@...
To: LTspice@...
Subject: [LTspice] Re: Step Change to k of Coupled Inductors During

Transient Analysis

Date: Tue, 23 Jul 2013 14:35:32 -0000



--- In LTspice@..., "bordodynov" BordodunovAlex@ wrote:


Hi Alex. Updated your browser to a readable characterset? ;-)
Welcome!

hws

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

Can you change the circuit step by step so that you can see which modification causes the problems?

Best regards,

Frank

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.

Hello Jason,

Please try my suggestion with cshunt as I mentioned before.

Best regards,
Helmut

Hi,

in that article Mike Robins claims superiority of their "CircuitLab" simulator over all other simulators in respect of numerical resolution.



He shows a LTspice screen with a totaly off solution.

In fact this circuit needs the "alternate" solver to get the right solution.

Is there a secret .option for seting the solver?

Help says:
"There is no .option to specify which solver is used, the choice must be made before the netlist is parsed because the two solvers use different parsers."

Why not?
Wouldn't it be better than puting a text on the shematic, saying "attention: switch to alternate solver for this deck".

Greetings
Michael

--- In LTspice@..., "jason.vanryan" <andrewc.russell@...> wrote:

--- In LTspice@..., "analogspiceman" <analogspiceman@> wrote:

--- In LTspice@..., "jason.vanryan" <andrewc.russell@> wrote:

Thanks for the feedback. This is happening on the latest version
I downloaded and after I have set all sim variables to default in
the tool tab.

I will try the cap idea and see how it works out.

Be sure to try using the Alternate Solver as Andy suggested.
This option must be set manually (cannot be set in the simulation
commands on the schematic) and it is easy to overlook it having
been set on a prior, unrelated simulation. If it gets inadvertently
reset, marginal simulations can "suddenly" cease to run.

Clear- thanks for pointing that out. I'll give it a try.

My problems are still with me.

I have tried the ideas above still no success. I took a circuit that is simulating well and appears to be stable ( ie no convergence problems) that uses the same models as the previous circuit. I modify this circuit so that it is a replica of the first circuit discussed above, and the problems return. I am getting pages of ''Heightened Def Con from xxx to yyy' messages in the error log file which I never had before.