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There is a special very hot place reserved for supervisors who set students problems that the supervisor doesn't know how to solve.?

You might do better to use LTspice, but work only with the .ASC and models you can find in the group's archives (the folders with names beginning with 'z...' on the Files page), together with advice from Andy and others. Or, if you know, or you supervisor will tell you, which foundry would make the device you design, you can ask the foundry for 20nm models.

We can't help with Hspice or any other version of SPICE.

I am just a student and half of the things you said went bouncer T-T. My HoD told me to make this project because i attended Semi-conductor training program in SVNIT SURAT. Even he don't know how to build this circuit and he want me to build and i am ready ofc, because i love vlsi and designing, but if i know nothing about it how should i do that. not giving excuses tbh. i def want to learn that's why i came here. i'll try to send the file?

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Read the message! BOLD TYPE

How should I upload ?

On Fri, Apr 4, 2025, 6:40 PM John Woodgate via <jmw=[email protected]> wrote:

We can't help much unless you let us see more of what you are doing. Upload your .ASC file AND all the other files required to run the simulation, but not .RAW? and .LOG files or pictures,? in a ZIP archive to Files => Temp.

Go to the web page: /g/LTspice/topics. Click on Files in the list on the left. Then click on Temp. Then click on New Upload in the blue box at top left. Click on Upload File in the drop-down menu. Then send a message to tell us that you did that.

On 2025-04-04 13:59, siddhugoad via wrote:

I am trying to build 6T SRAM using 20nm but when i run the simulation i am having the errors saying parameter level = 72 and also other bunch of errors.

my 180nm file ran properly but when i tried for 20nm it's not working although i changed W/L ratio from L=0.18 ,W= 0.64 to L= 0.02 to W= 0.3.??

What should i do ?

--
OOO - Own Opinions only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion

Virus-free.

How should I upload ?

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We can't help much unless you let us see more of what you are doing. Upload your .ASC file AND all the other files required to run the simulation, but not .RAW? and .LOG files or pictures,? in a ZIP archive to Files => Temp.

Go to the web page: /g/LTspice/topics. Click on Files in the list on the left. Then click on Temp. Then click on New Upload in the blue box at top left. Click on Upload File in the drop-down menu. Then send a message to tell us that you did that.

I am trying to build 6T SRAM using 20nm but when i run the simulation i am having the errors saying parameter level = 72 and also other bunch of errors.

my 180nm file ran properly but when i tried for 20nm it's not working although i changed W/L ratio from L=0.18 ,W= 0.64 to L= 0.02 to W= 0.3.??

What should i do ?

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On 03/04/2025 09:26, jacfev via groups.io wrote:

My question is multiple:
1. What are the influential spice parameters that optimize the switching speed?
To my knowledge, it's mainly Bf that seems to be the most important for increasing the switching speed, which I vary like this:
.step param X LIST 100 150 200 250 300
.model myModel AKO: 2N2222 NPN (Bf={X})
2. What measurement (equation) can be used to measure the speed?
3. What circuit should I use to compare the switching speed results as a function of the influential parameter?

This is not such a simple question. What are your parameters for switching speed? Presumably rise and fall times? How about delays times? You can still have fast rise and fall times, but with a significant delay time if the transistor is driven into saturation.

I would say that Bf is not one of the most influential parameters for speed. More important are the internal capacitances: Cje and Cjc, and transit times: Tf and Tr. Tr sets the reverse recovery time, i.e. charge storage in the base region on switch off - this is critical in saturated BJT switching circuits.

To assess the speed, you need to .MEAS the rise and fall times at the output, and the turn-on and turn-off delay times referenced to the input source waveform.

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I agree with Tony. If Bf is found to affect switching speed, we need to see the test circuit .ASC that you are using, because it's probably not the optimum.

On 03/04/2025 09:26, jacfev via groups.io wrote:

My question is multiple:
1. What are the influential spice parameters that optimize the switching speed?
To my knowledge, it's mainly Bf that seems to be the most important for increasing the switching speed, which I vary like this:
.step param X LIST 100 150 200 250 300
.model myModel AKO: 2N2222 NPN (Bf={X})
2. What measurement (equation) can be used to measure the speed?
3. What circuit should I use to compare the switching speed results as a function of the influential parameter?

This is not such a simple question. What are your parameters for switching speed? Presumably rise and fall times? How about delays times? You can still have fast rise and fall times, but with a significant delay time if the transistor is driven into saturation.

I would say that Bf is not one of the most influential parameters for speed. More important are the internal capacitances: Cje and Cjc, and transit times: Tf and Tr. Tr sets the reverse recovery time, i.e. charge storage in the base region on switch off - this is critical in saturated BJT switching circuits.

To assess the speed, you need to .MEAS the rise and fall times at the output, and the turn-on and turn-off delay times referenced to the input source waveform.

--
Regards,
Tony

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Gentlemen, those CD4x and 74HC libraries have two required values that appear on a symbol's SpiceModel line.

ctrl-right-click a logic symbol to alter its SpiceModel line.

By default the two values are the nodes "VDD" and "0".

Creating a 12V power supply for CD4x logic and naming its output node VDD works out-of-the-box.

But assume for example, you already have a V-24 node and a V-12 node that could power the logic.

Change the logic symbol's default SpiceModel value from "VDD 0" to "V-12 V-24".

This sets logic outputs to be V(V-12)=logic-high and V(V-24)=logic-low, instead of VDD/0.

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In either case the difference across the power pins is 12 volts, -12 to -24 volts or 12 to 0 volts has the same 12 volt difference.

To power the internal logic from 12 volts, change the symbol's default SpiceLine (not SpiceModel) value from VDD=5 to VDD=12.

The SpiceLine VDD=x value sets the model's power-pin voltage and can be anything like VDD=2.3 or 3.5, 6, 12 etc...

The three SpiceLine values control functions within the logic like, prop-delay, output drive, slew rate, etc...

The SpiceLine SPEED=1.0 and TRIPDT=5e-9 are defaulted for the logic family.

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Changing the VDD=x value affects the speed of a given device. (i.e. CD4x is much faster at 15V than it is at 5V)

The SpiceLine SPEED=1.0 value is relative.

To model CD4x-like logic at 12 volts that is 10 times faster than normal CD4x logic, change the SpiceLine SPEED=1.0 value to SPEED=10.

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My question is multiple:
1. What are the influential spice parameters that optimize the switching speed?
To my knowledge, it's mainly Bf that seems to be the most important for increasing the switching speed, which I vary like this:
.step param X LIST 100 150 200 250 300
.model myModel AKO: 2N2222 NPN (Bf={X})
2. What measurement (equation) can be used to measure the speed?
3. What circuit should I use to compare the switching speed results as a function of the influential parameter?

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Those messages are not significant LTspice error messages. They are probably due to over-keen syntax checks that were introduced in some 24.1.x versions of LTspice. I don't see them in my .LOG file, which is not a surprise, because they include a path that only exists on your computer. Which version of LTspice are you using?

I can't see why you can't probe the circuit, of course, but you can't probe pins that have no wire attached. Can you plot the voltage on the wire connected to Qbar of U2, for example?

At the end of the log file I get the following and cannot probe the circuit. I know it is a short run-time circuit. It is a portion of a larger one, and I have not played with the digital stuff before.

----------------------------

T:\Other drawings\XM27 gun\41897800 Elec Sys Assy\41897801 Ctl Box\41897802 Control box\41897817 K3 Relay assy\A154\simulation\cd4000_v.lib(91): syntax error
.param td1=1e-9*(400-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
T:\Other drawings\XM27 gun\41897800 Elec Sys Assy\41897801 Ctl Box\41897802 Control box\41897817 K3 Relay assy\A154\simulation\cd4000_v.lib(92): Expected ")" here.
.param td2=1e-9*(250-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
T:\Other drawings\XM27 gun\41897800 Elec Sys Assy\41897801 Ctl Box\41897802 Control box\41897817 K3 Relay assy\A154\simulation\cd4000_v.lib(92): syntax error
.param td2=1e-9*(250-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
T:\Other drawings\XM27 gun\41897800 Elec Sys Assy\41897801 Ctl Box\41897802 Control box\41897817 K3 Relay assy\A154\simulation\cd4000_v.lib(93): Expected ")" here.
.param td4=1e-9*(130-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^
T:\Other drawings\XM27 gun\41897800 Elec Sys Assy\41897801 Ctl Box\41897802 Control box\41897817 K3 Relay assy\A154\simulation\cd4000_v.lib(93): syntax error
.param td4=1e-9*(130-40-10)*5.0/(vdd1}*{speed1}
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^^^