开云体育

More recent note -

Two more mosfet rectifier controllers in the last few months:

LM5050 from National Semiconductor is a 6-pin orring controller
introduced in Oct 2010, with functionality similar to LTC4357, but no
attempt of pin-pin compatability. It adds diagnostic functions via the
6th pin.
LM5050-2 data:
LM5050 app:

FAN6204 also makes a late entry from Fairchild/Samsung, an SO8 with
functionality similar to ZXGD3101, with near pin-pin compatability. It
prescribes external resistors to the drain voltage sensing pin.
FAN6204 data:

Modeling the simple normally-off rectifier controller (or any other)
becomes interesting when package parasitics are included. A T0220 or
D2, for example, can show between 5 and 10nH on gate and source pins.
All those spice simulations where anything happens in 10s of
nanoseconds???? fugedabaddit!

--- In LTspice@..., "boid_twitty" <legg@> wrote:

--- In LTspice@..., "boid_twitty" <legg@> wrote:

Rick,

The component values used in the IRF6618 subcircuit
from IR use an internal gate resistance of ~1.73 ohms,
so the 1A of gate current simulated would easily allow
internal gate thresholds to exceed 2V4 during dV/dT.

The standard mos parameters used in the LT model assign
this a 3ohm value, which will produce a similar effect.
It is also almost noticable on simulations where the
unenhanced mos gate is shunted with 10R.

Should have seen it sooner. In real life, hard switching,
it's noticable as a difference between positive-going and
negative-going gate drive plateau levels, measured on the
fet package gate terminal.

Thanks for pointing it out.

If you edit the LT standard model for this part, so that Rg
becomes 3m (1000 times smaller), then restart LTSpice to
load the new standard.mos values, the same sync rec drive
circuit is much more severely stressed. As drawn, it bottoms
out at 7.5A drawn from the gate, rather than the previous 1A,
due to the almost unlimited dV/dT of which the ideal switch is
capable.

I've already pretty much given up on simulating this circuit,
simply due to the questions concerning stored charge.

Your assertion - that simply by turning a fet, on the stored
charge in the body diode is removed, is unfortunately
inaccurate. I'd be happy if it were true.

In real component testing of simple rectifiers, stored charge
does not begin to be swept out until voltage reversal occurs.
As the rectifier does not support a blocking voltage until the
charge is swept out, the reverse voltage is small, but continuously
present until the snap-off.

This being the case, not only will charge be stored, but a
peak charge representative of peak current memory is
present that makes synchronous rectifier sensitive to body
diode currents that may occur before enhancement is
achieved.

I have to do physical testing to determine the extent of
this characteristic in typical parts for circuits in which the
self-synchronizing rectifier may have use. This may determine
the practical frequency limit for any topology/chemistry of
end-use configuration.

RL

--- In LTspice@..., "Rick" <sawreyrw@> wrote:

Your circuit is strange, but here's what's happening.
When the switch closes (BTW, it doesn't close in zero time.
Also remove the SW designator from the switch; you are
using pl.) the drain current increases to the point where
the transistor comes out of saturation and the drain
voltage increases.

You are referring to the enhanced mosfet simulation.
SR5a004off-Lstep.asc

In this simulation the mosfet is not saturated, when
the upper switch turns on. It is at a regulated negative
voltage.

The switch initially causes the negative fet current
and voltage to 'reduce' towards zero.

This in turn causes the external gate voltage (Vg) to
fall.

Drain voltages moving towards zero cause the regulator
to reduce gate drive in an attempt to regulate the
'reducing voltage' - to maintain a 'higher' negative
value.

However, the internal gate voltage is still
high enough to keep the MOSFET conducting. Look at
the current coming out of the gate to understand that
the internal gate node is still being discharges.

If you expand the plot to full screen, you will see
that the gate voltage always reaches 1V (the 'off'
voltage for this circuit) before the drain current
passes through zero. The fet is off.

Any gate current flowing is through Cdg, as the drain
voltage rises.

Eventually the MOSFET will turn off. There is no
current through the body diode during the time
interval I just described.

I agree that no body diode current flows during the
illustrated transition. My inquirey was to the
origins of the drain current drawn from the fet,
when gate voltage is clamped to 1V.

There IS body diode current flow during the Ton
transition, in the same simulation, but at a
different time interval, not shown here.
Theoretically this forms stored charge that
would remain until the turn-off, when it is
finally swept out.

With no diode stored charge being modeled, there
is no source of charge to provide the current that
is shown to flow in the Toff time period of the
simulation we're talking about.

If there is no reverse recovery modeled, where does
this current spike originate? In amplitude it compares
to currents flowing to sweep out charge in the diode-
only simulation, though it's shape is non-characteristic
of reverse recovery.

If the Fet gate is held off all the time, and the
recovery-free diode body alone conducts, the same
charge is not present.

RL

Hi,

I've been playing with the current source element with the 'active load' box checked. I place this in series with a voltage source and a resistive load (e.g. to model a PSU with current limit) and ramp up the voltage.

The load current flattens out as expected once it reaches the current source set point, but below this point the current source behaves as a resistor with value (1/I_set). Is there any way to change this behaviour, or does it behave this way for compatibility with other variants of SPICE?

More generally, is there a better way to model a PSU with a current limit that doesn't impose any voltage drop until the current limit is reached?

TIA

R.

Long long ago and far far away, I designed varactor triplers for 100 watt
transmitters to go from 150 MHz to 450 MHz. Even in the day I had some kind
of model for the varactor for the pre-SPICE analysis program. The
fundamental idea was to generate harmonics via the diode followed by a dual
helical coil filter. Like I said ... long long ago.

The performance of the varactor is directly influenced by the minority
carrier lifetimes of the device. The vendor once "improved" the product.
This was shortening the minority carrier lifetime ... aka switching faster.
Needless to say this prevented my tripler from working. Zapping the parts
in a van degraff generator sufficiently damaged the higher performing
varactors to acceptably allow my tripler to work again. The product line
was shut down until the quickest solution was found.

Ok. So off subject, but this reminded me of the past.

What are anti-pallell PIN diodes? Conceptually.

On Mon, Jul 15, 2013 at 6:12 PM, jmulchin1 <jmulchin@...> wrote:

**


I'm trying to design a 240MHz to 720MHz tripler circuit and wonder if
anyone has an example circuit I could follow. The goal is to use
anti-parallel PIN diodes, so an example using PIN diodes would be helpful.

Thanks for any help
Jerry

--
Jeffrey L Walden

EMC/SI RF analysis and product development

jwalden@...
(866)547-5365