--- In LTspice@..., "redblack001" <news@...> wrote:
More generally, is there a better way to model a PSU with a
current limit that doesn't impose any voltage drop until the
current limit is reached?
There are probably dozens of ways to do this in LTspice. Here is
one way that uses just one device (a V-I table I-source):
I1 0 1 TBL(-5 0 {1u-5} 1 0 1) ; 5V 1A PSU with 1uV of droop
R1 0 1 R=1u+time**2 ; behavioral resistor used as a test load
.tran 10
