开云体育

Helmut,

Thank you for your generous response. Your answer may well solve my problem.

But I am wondering where I might find the exact syntax for defining different AC and transient values for a resistor. Could you point me in the right direction for such documentation? I don't seem to see it in the scad3.pdf file.

Thanks

--- In LTspice@..., Helmut Sennewald wrote:

I only know of the resistor which allows a different value in the
AC simulation.

Instead of a value of 1kOhm in all types of simulation, 1k, you
can have a a different value in the AC-simulation. 1k ac=10k

I think I know what the original poster was getting at. He would
like to switch models based on the type of analysis. For example,
one might try to make a switched mode power supply that used an
averaged model for an .ac analysis and a fully switched model for
a .tran analysis. Perhaps this is a bad example because it can't
easily be done just at the control IC level, but would require
modifying the power stage as well. Anyway, there are other perhaps
more effective ways to do this by switching between using a digital
or continuous duty cycle control node (0<d<1). There are examples
of this technique in our files section.

In any case, one could use two analysis dependent resistors to
make a SPDT switch to chose between two circuit models. Maybe an
example where this would make more sense might be for a transformer
winding model, which could switch between a Laplace version for .ac
and a lumped approximation for .tran. -- a.s.

On 9/7/2012 7:08 PM, Malcolm Smith wrote:

Kerry
The Book chapter written by Jim Williams who I think wrote the
application note you suggested put the chapter together from such
application notes but the book is quite recent while the application
note is quite old. however a lot of he info is indeed in the free
application note.

Even though "Analog Circuit Design" Edited by Bob Dobkin and Jim
Williams was published in 2011 the Publisher's Note in the book says:

"This book was compiled from Linear Technology Corporation's original
Application Notes. These Application Notes have been re-named as
chapters for the purpose of this book."

A cross reference in the book shows Chapter 34 "A seven-nanosecond
comparator for single supply operation" is Application Note 72.

Howard

Somewhere on the web is a paper comparing op amps with comparators and
is good reading . high speed comparators of 10ns and less rise time
need proper consideration to hardware layout.

Regards
Malcolm

--- In LTspice@..., "RobertS" <rstevescott@...> wrote:

Hi. I've got a quick question. I've looked on this site and scad3.pdf but haven't found anything... could be it's just hard to pick the right keywords.

Is there any built-in function that I can use to determine the type of analysis being run, for example, .tran, .ac, etc.?

I've run into a problem where one of my "B" type current sources works fine in .tran analysis, but does not seem to incorporate a correct response in AC analysis. I've found some messages related to this (but I still don't fully understand the limitations involved).

In any case, I can solve my problem by using different methods to calculate separate circuit output voltages for .tran and .ac analyses. But this relies on users to understand and choose which output to use. My experience is that people often ignore even written warnings about model usage. So I'd like to create an "if" type function that yields different answers depending on whether the analysis type is AC or not.

Anyone have suggestions?

Thanks.

Hello,

I only know of the resistor which allows a different value
in the AC simulation.

Instead of a value of 1kOhm in all types of simulation,
1k
you can have a a different value in the AC-simulation.
1k ac=10k

Best regards,
Helmut

--- In LTspice@..., "Helmut" <helmutsennewald@...> wrote:

--- In LTspice@..., "vittorio pomo" <VITTORIO_POMO@> wrote:

Thank you Helmut

Could you, pleas,let me know the procedure step by step to
obtain the output foldback function for the circuit of your
example? I understand I have to run
the .asc file but i don't know which steps are necessary
after the temporal simulation

Thank you Best regards

Vittorio

Hello Vittorio,

The extra V-source and the diode are the load. I start with
a voltage higher than the unloaded output voltage. The diode
is reversed bias in this case and thus the current is zero.
When the test voltage source is below the unloaded regulator's
output voltage, the diode becomes conducted and quickly the
maximum current will flow. When I further decrease the voltage,
the current will be reduced due to foldback. If the load is
at 0V, the current will be at its minimum.

When I plot V(out), "time" will be on the x-axis.
Now I change the x-axis from "time" to "I(VL)" to get this
standard plot showing the foldback characteristic.

I just discovered that I only have to sweep VL from 15V to 0V.
See my latest circuit.

Files > Examples > Educational > foldback_simulation.zip

Best regards,
Helmut

Hello,

The foldback characteristic is defined by the resistors R7
and R4. If the output voltage is low, the Ube of Q2 will
become higher due to the extra current via R7. Thus less
voltage drop on R1 will be necessary to make Q2 active
(Ube>0.7V).

Best regards,
Helmut

Right you are. I disconnected the output capacitor and indeed current
goes to zero in the collector resistor.

That's one of the great things about LTspice. You can SEE that the
transistor's current goes to zero, even without disconnecting the
output capacitor. Just hover the mouse over the collector pin until
it turns into the ammeter icon, click, and see the collector current
waveform. On a workbench we tend to think only of voltages (because
they are easy to look at), but LTspice lets us look at things like
currents just as easily.

Andy

--- In LTspice@..., "vittorio pomo" <VITTORIO_POMO@...> wrote:

Thank you Helmut

Could you, pleas,let me know the procedure step by step to
obtain the output foldback function for the circuit of your
example? I understand I have to run
the .asc file but i don't know which steps are necessary
after the temporal simulation

Thank you Best regards

Vittorio

Hello Vittorio,

The extra V-source and the diode are the load. I start with
a voltage higher than the unloaded output voltage. The diode
is reversed bias in this case and thus the current is zero.
When the test voltage source is below the unloaded regulator's
output voltage, the diode becomes conducted and quickly the
maximum current will flow. When I further decrease the voltage,
the current will be reduced due to foldback. If the load is
at 0V, the current will be at its minimum.

When I plot V(out), "time" will be on the x-axis.
Now I change the x-axis from "time" to "I(VL)" to get this
standard plot showing the foldback characteristic.

I just discovered that I only have to sweep VL from 15V to 0V.
See my latest circuit.

Files > Examples > Educational > foldback_simulation.zip

Best regards,
Helmut

Andy wrote:

rainbowsally wrote:

No. Only saturating.

If you look again, there is more than just saturation going on. It
also clips on the output's positive peaks, due to Vbe falling below
that necessary to maintain conduction. The collector waveform clips
(though in a tilted fashion due to C2) as the collector current
completely cuts off for about 40% of every cycle. That explains why
both positive and negative peaks are distorted, but with a different
shape.

Right you are. I disconnected the output capacitor and indeed current goes to zero in the collector resistor.

And how this applies to ltspice (for those overly concerned about topic enforcement) is that you CAN do this without cutting traces on circuit boards with a razor blade but simply deleting a wire in our ltspice program. :-)

The file being discussed is (I got it again, yes, a single transistor).

racproj.asc in the files temp folder.

But the distortion waveform
isn't symmetrical, so it may not even biased correctly.

I think the main reason for that asymmetry is C2 discharging, at the
relatively low frequency.

Yup.

Are we even looking at the same circuit? I see only one transistor.
You seemed to be talking about two of them. ???

Andy

Yuh got me there. It was the same circuit but I misremembered how it was drawn.

Thank you Helmut

Could you,pls,let me know the procedure step by step to obtain the output
foldback function for the circuit of your exemple?I understand I have to run
the .asc file but i don't know which steps are necessary after the temporal
simulation

Thank you Best regards

Vittorio

Hi. I've got a quick question. I've looked on this site and scad3.pdf but haven't found anything... could be it's just hard to pick the right keywords.

Is there any built-in function that I can use to determine the type of analysis being run, for example, .tran, .ac, etc.?

I've run into a problem where one of my "B" type current sources works fine in .tran analysis, but does not seem to incorporate a correct response in AC analysis. I've found some messages related to this (but I still don't fully understand the limitations involved).

In any case, I can solve my problem by using different methods to calculate separate circuit output voltages for .tran and .ac analyses. But this relies on users to understand and choose which output to use. My experience is that people often ignore even written warnings about model usage. So I'd like to create an "if" type function that yields different answers depending on whether the analysis type is AC or not.

Anyone have suggestions?

Thanks.

--- In LTspice@..., "Shah" <shah_m_sharif@...> wrote:

Helmut,

After swapping the source and drain ( source is close to the gate) I am still getting similar AC current. If you have simulated this circuit is it possible to upload it?

Anohter slightly seperate quesiton, does LTspice auto calculate
AD,AS,PD,PS from the width and lenght and the mosfet model file or do I need to put values for AD,AS,PD,PS for more accurate AC current at high frequency?

Thanks,
Shah

Hello Shah,

No SPICE program can calculate AD,AS,PD,PS. You have to enter
these values, if you want take them into account. Even Cadence
can't calculate that. If it does, it's because you have entered
data about these sizes in another place in the design suite.

Still my question. Why L=1.2um in a 45nm process?

Best regards,
Helmut

--- In LTspice@..., "Helmut" <helmutsennewald@> wrote:

--- In LTspice@..., "shah_m_sharif" <shah_m_sharif@> wrote:

Hello,

I am running a simple simulation with two pmos devices.
They form a traditional cascode current source. Their gates are connected to dc voltage. The output of the current source goes to a
AC voltage source and I am measuring AC source current.

My circuit matches closely with cadence from DC simulation, however,
when I plot 1/(AC voltage source current) they are 10X off. I am wondering if I am setting up LTSpice the way it should be.

I have uploaded my circuit and mos model file in file are- file name is -LTC.zip
Please note I am using mos model=54 for this simulation.

Thanks for your help,
Shah

Hello Shah,

The Mosfets in your circuit are reversed. The source is the pin
near the gate in this symbol. Please rotate both Mosfets by 180°.
The AC current will then be 30% less.
I wonder why you use a 45nm technology with L=1.2um.

Best regards,
Helmut

Does this school-boy need to be told to read his books! Hey, I guess this guy is in university already.? Behave like an adult and do the work.? You are not 12.

Kerry
The Book chapter written by Jim Williams who I think wrote the application note you suggested put the chapter together from such application notes but the book is quite recent while the application note is quite old. however a lot of he info is indeed in the free application note.

Somewhere on the web is a paper comparing op amps with comparators and is good reading . high speed comparators of 10ns and less rise time need proper consideration to hardware layout.

Regards
Malcolm

Helmut,

After swapping the source and drain ( source is close to the gate) I am still getting similar AC current. If you have simulated this circuit is it possible to upload it?

Anohter slightly seperate quesiton, does LTspice auto calculate
AD,AS,PD,PS from the width and lenght and the mosfet model file or do I need to put values for AD,AS,PD,PS for more accurate AC current at high frequency?

Thanks,
Shah

In message <k2dmni+hnbn@...>, dated Fri, 7 Sep 2012, tonyatritecom <tony@...> writes:

You will normally get some help when you demonstrate you have made at least some effort towards solving your problem, even though many strongly disapprove in principle with students seeking help here with homework.

I think that it's OK to ask for *help*, but not to expect someone to provide complete answers. If I answer a homework enquiry, I try to guide the enquirer into the right thinking pattern towards the solution, often by asking questions in return, like, 'What does the data sheet say about the maximum supply voltage?'
--
OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk
The longer it takes to make a point, the more obtuse it proves to be.
John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UK

--- In LTspice@..., "aldingrard" <aldingrard@...> wrote:

Hello,

When I change the values in the the .tran command, the position of texts in plotting are often changing, and some are lost.

When I add plot or move a trace from a pane to another one, texts are also moving of an unwanted manner.

My aim is to add a short titel for easy identification to each of 6 to 12 simultaneous panes (for instance on the left of each, or at the center top of each), in order that their position in their proper pane stay unchanged after changing the .tran command, or adding a plot, or mouving a trace from a pane to another one.

Is that possible, and how to do it ?

Thanks for help.

Best regards. Gérard Aldin.

Hello Gérard,

Text and other freehand objects placed on a waveform pane remain fixed in the position you place them _relative_ to the plot axes. If the plot subsequently autoscales and they cease to be visible, they are just off-screen. Try zooming out until they reappear.

You can see where text and other objects are by opening the .plt file, if you have saved one. The x and y coordinates are saved there; you can edit them manually, if necessary.

Regards,
Tony

--- In LTspice@..., "dang quoc bao" <btdtknb_301192@...> wrote:

Hi all,
My name is Dang Quoc Bao. I am a student
My lab have a question that "Design two different DC bias circuits to provide a Q-point suitable for an amplifier.
Discuss your choice of operating point as well as the design of your circuits. In LTSpice, simulate your designs if the MOSFET threshold voltage VTN changes by +-20% and comment on the stability of the circuits". I need for your help

Thanks

Hello Dang Quoc Bao,

What you actually need is to read the home page of this group, and understand what it says.

We are not here to do your homework. If, in the course of doing your own homework you create some circuits using LTspice and have difficulty running them or interpreting the results, people here will be more than happy to help. That is, after all, why many of us are here in the first place.

You will normally get some help when you demonstrate you have made at least some effort towards solving your problem, even though many strongly disapprove in principle with students seeking help here with homework. On the positive side, at least you're honest enough to freely admit you are a student seeking homework help.

Regards,
Tony

--- In LTspice@..., "shah_m_sharif" <shah_m_sharif@...> wrote:

Hello,

I am running a simple simulation with two pmos devices.
They form a traditional cascode current source. Their gates are connected to dc voltage. The output of the current source goes to a
AC voltage source and I am measuring AC source current.

My circuit matches closely with cadence from DC simulation, however,
when I plot 1/(AC voltage source current) they are 10X off. I am wondering if I am setting up LTSpice the way it should be.

I have uploaded my circuit and mos model file in file are- file name is -LTC.zip
Please note I am using mos model=54 for this simulation.

Thanks for your help,
Shah

Hello Shah,

The Mosfets in your circuit are reversed. The source is the pin
near the gate in this symbol. Please rotate both Mosfets by 180°.
The AC current will then be 30% less.
I wonder why you use a 45nm technology with L=1.2um.

Best regards,
Helmut

--- In LTspice@..., "aldingrard" <aldingrard@...> wrote:

Hello,

When I change the values in the the .tran command, the position of texts in plotting are often changing, and some are lost.

When I add plot or move a trace from a pane to another one, texts are also moving of an unwanted manner.

My aim is to add a short titel for easy identification to each of 6 to 12 simultaneous panes (for instance on the left of each, or at the center top of each), in order that their position in their proper pane stay unchanged after changing the .tran command, or adding a plot, or mouving a trace from a pane to another one.

Is that possible, and how to do it ?

Thanks for help.

Best regards. Gérard Aldin.

Hello Gérald,

I don't think it's possible as far as I know.
You could send an email with your suggestion/wish to the
email-address in the Help->About of the LTspice program.

Best regards,
Helmut

--- In LTspice@..., "vittorio pomo" <VITTORIO_POMO@...> wrote:

Hi Helmut

Is it possible to use LTspice to plot a power supply output
characteristic (Foldback e.g.)?

Thank you

Vittorio

Hello Vittorio,

Yes you can. :-)

You could use a V-source with an ideal diode as load. When you
sweep this VLoad-source, you will get the foldback characteristic.
Just plot plot V(output) versus I(VLoad-source).

I made an example.

Files > Examples > Educational > foldback_simulation.zip

Best regards,
Helmut