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Re: "Timestep too small" error while simulation
Helmut,
Mike, could you tell us what tolerance is used inThe tolerances that are typically most useful to loosen are abstol, vntol, and chgtol. If you loosen reltol, it's best not to loosed it too much. The "No Bypass" check box is also often an important nerve to try, especially if there are bipolar transistors in the circuit. Which tolerances are used by which analysis types: .op .dc .tran .ac .noise abstol yes yes yes no no vntol yes yes yes no no chgtol no no yes no no reltol yes yes yes no no trtol no no yes no no sstol no no no no no Note that .ac does not use any tolerances. It just does linear(complex) math as accurate as double precision allows. However, it's doing this on a linearized version of the circuit from a .op and the tolerances are used to find that solution for non-linear circuits. Sstol is steady state tolerance and is only used to set how critical the steady state detector should be. Usually this means how close the error amp current must be to zero before be considered close enough to zero. It's only used when the keyword "steady" is on the .tran command and has no impact on the accuracy of the simulation. Trtol is sort of interesting because it does not impact directly any accuracy but modifies the strategy of the .tran integrator. This is typically set to 7(it has no units) in other SPICE's. I set it to 1 in LTspice because all those SMPS macro models run better that way -- with no apparent simulation artifacts for novice users. If you do transistor level simulations, then it's probably better to loosen trtol some. --Mike __________________________________________________ Do you Yahoo!? Yahoo! Shopping - Send Flowers for Valentine's Day |
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Re: "Timestep too small" error while simulation <[email protected]>
Peter Kapas
Reiner,
I got the same or similar error message, when I tried to simulate a square-root circuit model. Of course, it is a big different between applications, but maybe good to know, why happened it. The reason was the negative value "under" sqrt, what is imaginary number. :) . Peter |
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Re: Trying to use SIDAC library
--- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote: --- In LTspice@..., "Helmut Sennewaldabout circuitHello Bunny,this I used the DIAC symbol from the LT library, renamed it andsaved ok ...". There is always hope! Helmut, why are you so smart? Worked great thanks. |
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Re: "Timestep too small" error while simulation
--- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote: --- In LTspice@..., Panama Mike <panamatex@y...> wrote:Hello Gents,Rainer,Hello Mike,I'm using scad3 for a few weeks and I'm very happyIt means the solver failed to converge for the Perhaps I can help here. Fixing convergence problems can be a complex business but here is a sequence of things to try which has been found useful by many Spice users. It applies to .TRAN convergence problems which occur some way into the simulation rather than at the beginning. The list is in order of usefulness and should be tried in this order. 1) Check your circuit! Correct any drafting errors and be sure that there are no design errors. 2) Set RELTOL to .01 in the SPICE tab of the Control Panel (default = .001).This trades off a little precision but speeds up the simulation. 3) Set .OPTIONS ITL4=100 (default=10) This increases the number of iterations at each time step before SPICE gives up. 4) Set ABSTOL to 1E-9 (default 1E-12) and VNTOL to 1E-3 (default 1E- 9). Both of these parameters are on the SPICE tab of the Control Panel. They reduce the required precision slightly to make the transient solution easier to find. The default values are intended for use with IC designs. The vales suggested here are more appropriate for power supply circuits. 5) Add realistic parasitics to your circuit. e.g. 3pF across diodes and 5pF across BJT's. Add 100MEG to 1G resistors from each node to ground. (Unfortunately LTSpice does not appear to have the RSHUNT .OPTIONS parameter which would do this automatically). 6) Change the integration method to Gear (default is modified trap). This parameter is also found on the SPICE tab of the Control Panel. It should be used in conjunction with RELTOL = .01. Gear integration tends to produce more stable if slightly less precise results than trapezoidal integration. It is the preferred method for simulating power circuitry as it performs better in situations where there is ringing. I hope this helps. Russell |
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Re: "Timestep too small" error while simulation
--- In LTspice@..., Panama Mike <panamatex@y...> wrote:
Rainer,Hello Mike,I'm using scad3 for a few weeks and I'm very happyIt means the solver failed to converge for the Rainer could reduce the tolerances for the simulator in the Control Panel -> SPICE box by a factor of 10 to 100. Mike, could you tell us what tolerance is used in what type of simulation? I assume an .AC run doesn't use all of the tolerance settings used in .TRAN simulation. I would try the settings below. I am shure not all changes are useful. Please give us a recommendation Mike. Example: -------- Abstol 1e-12 -> 1e-10 Reltol 1e-3 -> 1e-2 Chgtol 1e-14 -> 1e-12 TRtol 1 Voltol 1e-6 -> 1e-4 SStol 1e-3 -> 1e-2 Best Regards Helmut |
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Re: Trying to use SIDAC library
--- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote: --- In LTspice@..., "bunnyblues2001help somewhere.file and the previous posts. I guess we all have to start Hello Bunny,saved my last sentence could be misleading . "No" refers to "Is the circuit ok ...". There is always hope! Best Regards, Helmut |
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Re: Trying to use SIDAC library
--- In LTspice@..., "bunnyblues2001
<bunnyblues2001@y...>" <bunnyblues2001@y...> wrote: I have no experience with Spice and what I know comes from the helpsaved Hello Bunny, I downloaded this library directly from Teccor. Click on "SIDAC" and download the library. It contains the library file "SIDAC:LIB" where you will find amomg others the "K1100E70". Please use this original library. Either you rename it to then to DEMSIDAC.LIB or you have to change the name in your ".include" statement to ".include SIDAC.LIB" . it to the symbol folder. I dropped it on my schematic and opened upIt's ok, but you could also move your cursor over the text DIAC and right-click your mouse. Replace the word DIAC with K1100E70. (K1100E70 is the model in the library). On the schematic I droppedStill all perfect. But it was not done in your attached file. It still has the value "DIAC" there. When I run the circuit I get anNo, the circuit is ok and will run perfectly after I really changed "DIAC" to "K1100E70". I have attached the corrected file and again, please download the SIDAC library from the above mentioned original source. Best Regards, Helmut Version 4 SHEET 1 892 692 WIRE -64 272 64 272 WIRE -96 272 -64 272 WIRE -64 336 -64 352 WIRE -64 352 64 352 WIRE -720 352 -720 368 WIRE -64 352 -304 352 WIRE -720 272 -304 272 WIRE -304 272 -176 272 WIRE -304 336 -304 352 WIRE -304 352 -720 352 FLAG -720 368 0 SYMBOL C:\Program\Files\LTC\SwCADIII\lib\sym\voltage -720 256 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 24 132 Left 0 SYMATTR Value EXP(0 1000 0 1.2us 10us 50us) SYMATTR SpiceLine Rser=.1 Cpar=.01uf SYMATTR InstName V1 SYMBOL C:\Program\Files\LTC\SwCADIII\lib\sym\ind -192 288 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L3 SYMATTR Value 10? SYMBOL C:\Program\Files\LTC\SwCADIII\lib\sym\res 48 256 R0 SYMATTR InstName R1 SYMATTR Value 1 SYMBOL C:\Program\Files\LTC\SwCADIII\lib\sym\polcap -80 272 R0 WINDOW 3 24 64 Left 0 SYMATTR Value 1.4? SYMATTR InstName C2 SYMATTR Description Capacitor SYMATTR Type cap SYMBOL C:\Program\Files\LTC\SwCADIII\lib\sym\Misc\DIAC -336 272 R0 SYMATTR InstName U1 SYMATTR Value K1100E70 TEXT -754 408 Left 0 !.tran 0 .001s 1us 1us TEXT -480 464 Left 0 !.include demsidac.lib |
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Re: "Timestep too small" error while simulation
Rainer
Mike,
thanks, for the quick answer! I played a little around and I was able to complete simulate the circuit. The wave-results are not as I wanted and I think I need a lot more simulations until my circuit will work. PM> can only stipulate a smaller one. You might PM> try the keyword "startup" on the .tran PM> command since it looks like your having PM> trouble with the intial conditions of your PM> simulation. When I got another timestep error, LTspice ran a few time (3ms of desired 10ms), until the error occurs. Are the data "in front of" the error correct? Am I near some limits of the simulator, that causes the problems of convergence? Are there some serial/parallel R/C/L I need to take care about? Can I trust it? Sorry for that elementary questions. I thought simulating a circuit is easier... :-) Gru, Rainer |
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Trying to use SIDAC library
I have no experience with Spice and what I know comes from the help
file and the previous posts. I guess we all have to start somewhere. What I wanted to do was call up a model from a sidac library downloaded from Intusoft. With no better ideas on how to go about this I used the DIAC symbol from the LT library, renamed it and saved it to the symbol folder. I dropped it on my schematic and opened up the Component Attribute Editor. In the value field I typed K1100E70 (K1100E70 is the model in the library). On the schematic I dropped a Spice directive .inc demsidac.lib. When I run the circuit I get an error message `Multiple instances of "any". So is there `any' hope for me? Version 4 SHEET 1 892 692 WIRE -64 272 64 272 WIRE -96 272 -64 272 WIRE -64 336 -64 352 WIRE -64 352 64 352 WIRE -720 352 -720 368 WIRE -64 352 -304 352 WIRE -720 272 -304 272 WIRE -304 272 -176 272 WIRE -304 336 -304 352 WIRE -304 352 -720 352 FLAG -720 368 0 SYMBOL C:\Program\ Files\LTC\SwCADIII\lib\sym\voltage -720 256 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 24 132 Left 0 SYMATTR Value EXP(0 1000 0 1.2us 10us 50us) SYMATTR SpiceLine Rser=.1 Cpar=.01uf SYMATTR InstName V1 SYMBOL C:\Program\ Files\LTC\SwCADIII\lib\sym\ind -192 288 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L3 SYMATTR Value 10? SYMATTR SpiceLine Ipk=3.9 Rser=0.038 Rpar=94000 Cpar=2.8p mfg="Coilcraft" pn="DO3316P-103" SYMBOL C:\Program\ Files\LTC\SwCADIII\lib\sym\res 48 256 R0 SYMATTR InstName R1 SYMATTR Value 1 SYMBOL C:\Program\ Files\LTC\SwCADIII\lib\sym\polcap -80 272 R0 WINDOW 3 24 64 Left 0 SYMATTR Value 1.4? SYMATTR InstName C2 SYMATTR Description Capacitor SYMATTR Type cap SYMATTR SpiceLine V=50 Irms=2 Rser=.007 MTBF=0 Lser=0 ppPkg=0 SYMBOL C:\Program\ Files\LTC\SwCADIII\lib\sym\Misc\DIAC1 -336 272 R0 SYMATTR InstName U1 TEXT -754 408 Left 0 !.tran 0 .001s 1us 1us TEXT -480 464 Left 0 !.include demsidac.lib * C:\Program Files\LTC\SwCADIII\My circuits\filter.asc V1 N002 0 EXP(0 1000 0 1.2us 10us 50us) Rser=.1 Cpar=.01uf L3 N002 N001 10? Ipk=3.9 Rser=0.038 Rpar=94000 Cpar=2.8p mfg="Coilcraft" pn="DO3316P-103" R1 N001 0 1 C2 N001 0 1.4? V=50 Irms=2 Rser=.007 MTBF=0 Lser=0 ppPkg=0 XU1 N002 0 K1100E70 .tran 0 .001s 1us 1us .include demsidac.lib .backanno .end |
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Re: "Timestep too small" error while simulation
Rainer,
I'm using scad3 for a few weeks and I'm very happyIt means the solver failed to converge for the circuit. Usually you have to change some aspect of the circuit to get it to run right. The 1533 is pretty complicated since it controls the slew rate of switching via local feedback loops. If you can't get it to run, you can e-mail the circuit to the address on the help=>about box for help with it. Note today is a holiday in the USA. I tried to modify the .tran command toYou can't tell it to use fewer timesteps. It solves for a maximum timestep. You can only stipulate a smaller one. You might try the keyword "startup" on the .tran command since it looks like your having trouble with the intial conditions of your simulation. --Mike __________________________________________________ Do you Yahoo!? Yahoo! Shopping - Send Flowers for Valentine's Day |
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"Timestep too small" error while simulation
bahrrainer <[email protected]>
Hallo,
I'm using scad3 for a few weeks and I'm very happy about the power and speed of simulation. Now, I tried a more complex simualtion with a LT1533 (I modified the sample) and got the following error: Analysis: Timestep too small; time=0.000173642, timestep=1.25e-019: trouble with node "n001" What does that mean and how can I prevent this error. I tried to modify the .tran command to use less steps, but this doesn't help. Thanks, Rainer |
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Re: Analog MUX
--- In LTspice@..., "Helmut Sennewald
<helmutsennewald@y...>" <helmutsennewald@y...> wrote: Sorry, I forgot the test circuit file. Helmut My test circuit(lv_4051.cir). ----------------------------- .OPTIONS ACCT LIST OPTS ITL5=25000 NOMOD * Nominal parameters .INC lvnomi.cir XLV4051 2 3 4 5 1 0 SWI1 VCC 1 0 DC 4.5 VINCTL 2 0 PULSE 0 4.5 5N 5N 5N 500N 1000N VINSIG 3 0 PULSE -1 4.5 100N 5N 5N 200N 500N RZ 4 0 1K CL 4 0 20P VEE 5 0 DC -1.5 .TRAN 1000N .END |
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Re: Analog MUX
--- In LTspice@..., "polapart <sahawley@m...>"
<sahawley@m...> wrote: I was looking around for a model of a low voltage MUX like theit up and it ran fine with DC control input, but when I attempted tofunctional part model.Hello, unfortunately I don't know any other source of SPICE model for this part. The behaviour looked indeed strange. It was ok with static driven control input, but failed with a pulse source. I already speculated about a problem of LTSpice. The last resort was to sketch the circuit from the netlist through all levels of subcircuits. That was a hard work and I wouldn't have done it, if I hadn't feared a problem of the LTSpice simulator. I found an inverter output connected to no other stage in the used subcircuit LLCN. The subcircuit levels are SWI1 -> LLCN. This circuit contains a first inverter, a two stage level shifter and two more following inverters. The output of the first inverter was connected to no other circuit. Obviously this is wrong. Either MP1 or MP2 has to be connected to node '4'. I supposed MP2. The simulation now runs with pulse sources as expected. Conclusion: There is a bug in this Philips model. This is really a pain and now I have low confidence about the quality of this library. It is in zhree files: Lvnomi.cir, lvfast.cir, lvslow.cir . I suppose to change the line in the .subckt LLCN ... MP2 6 2 50 50 MLVPEN W=135U ....... to MP2 6 4 50 50 MLVPEN W=135U ....... The interested reader can draw the schematic from the netlist. Hope that helps and please next time an easier problem. Best Regards Helmut Original subcircuit in file lvnomi.cir, lvfast.cir and lvslow.cir: ------------------------------------------------------------------ .SUBCKT LLCN 2 3 40 50 60 * LEVEL CONVERTER * INA = 2, OUT = 3, VEE = 40, VCC = 50, GND = 60 MP4 4 2 50 50 MLVPEN W= 30U L= 2.4U AD=120P AS=120P PD= 40U PS= 30U MN4 4 2 60 60 MLVNEN W= 15U L= 2.4U AD= 60P AS= 60P PD= 20U PS= 15U MP1 5 2 50 50 MLVPEN W=135U L= 2.4U AD=500P AS=500P PD=100U PS=135U MP2 6 2 50 50 MLVPEN W=135U L= 2.4U AD=500P AS=500P PD=100U PS=135U MN1 5 6 40 40 MLVNEN W=6.4U L=18.8U AD= 25P AS= 25P PD= 20U PS=6.4U MN2 6 5 40 40 MLVNEN W=6.4U L=18.8U AD= 25P AS= 25P PD= 20U PS=6.4U MP3 7 6 50 50 MLVPEN W= 10U L= 4.0U AD= 40P AS= 40P PD= 20U PS= 10U MN3 7 6 40 40 MLVNEN W= 5U L= 4.0U AD= 20P AS= 20P PD= 10U PS= 5U MP5 3 7 50 50 MLVPEN W= 30U L= 2.4U AD=120P AS=120P PD= 40U PS= 30U MN5 3 7 40 40 MLVNEN W= 15U L= 2.4U AD= 60P AS= 60P PD= 20U PS= 15U .ENDS Corrected subcircuit -------------------- .SUBCKT LLCN 2 3 40 50 60 * LEVEL CONVERTER * INA = 2, OUT = 3, VEE = 40, VCC = 50, GND = 60 MP4 4 2 50 50 MLVPEN W= 30U L= 2.4U AD=120P AS=120P PD= 40U PS= 30U MN4 4 2 60 60 MLVNEN W= 15U L= 2.4U AD= 60P AS= 60P PD= 20U PS= 15U MP1 5 2 50 50 MLVPEN W=135U L= 2.4U AD=500P AS=500P PD=100U PS=135U *** Changed node '2' to '4' in the next line *** MP2 6 4 50 50 MLVPEN W=135U L= 2.4U AD=500P AS=500P PD=100U PS=135U MN1 5 6 40 40 MLVNEN W=6.4U L=18.8U AD= 25P AS= 25P PD= 20U PS=6.4U MN2 6 5 40 40 MLVNEN W=6.4U L=18.8U AD= 25P AS= 25P PD= 20U PS=6.4U MP3 7 6 50 50 MLVPEN W= 10U L= 4.0U AD= 40P AS= 40P PD= 20U PS= 10U MN3 7 6 40 40 MLVNEN W= 5U L= 4.0U AD= 20P AS= 20P PD= 10U PS= 5U MP5 3 7 50 50 MLVPEN W= 30U L= 2.4U AD=120P AS=120P PD= 40U PS= 30U MN5 3 7 40 40 MLVNEN W= 15U L= 2.4U AD= 60P AS= 60P PD= 20U PS= 15U .ENDS |
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Analog MUX
polapart <[email protected]>
I was looking around for a model of a low voltage MUX like the
74lv4051. I found a a 6 pin fragment in the Philips LV library () called SWI1. I wired it up and it ran fine with DC control input, but when I attempted to toggle the switch with a square wave, once it turned off it never turned on again. Any ideas what's going on here and or pointers to a fully functional part model. Thanks SH |
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Re: Hierarchical schematics
--- In LTspice@..., Panama Mike <panamatex@y...> wrote:
Hello Mike,I put up a version today(2.00t) that enables nestedMany thanks for your help. I moved the Spice thank you very much for the work on solving the .lib problem in lower level hierarchy. Version 2.00x now works with the configuration from Ron, too. It is now no longer necessary to put the .include or .lib statement to the top level. Best Regards Helmut Let me sketch the three level hierarchy for the people interested: ------------------------------------------------------------------ Top: Level-1 schematic: ressitors, instance of level-2 Next Level-2: instance of level-3, resistors, opamp.asy .include opamp.sub Next Level-3: transistors, diodes, G-sources |
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Re: Digest Number 23
Peter Kapas
Hi Neil /New user: how to edit digital models?
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Show quoted text
----------------------------------------------- Try these: CD4093.asc ------------------------------------------------ Version 4 SHEET 1 892 692 WIRE 288 304 304 304 WIRE 160 320 112 320 WIRE 160 256 112 256 WIRE 160 272 128 272 WIRE 128 272 128 352 WIRE 128 352 160 352 WIRE 160 352 160 336 WIRE 160 352 240 352 WIRE 240 352 240 320 WIRE 160 352 160 368 FLAG 112 256 a IOPIN 112 256 In FLAG 112 320 b IOPIN 112 320 In FLAG 304 304 c IOPIN 304 304 Out FLAG 160 368 gnd IOPIN 160 368 BiDir SYMBOL C:\Program\ Files\LTC\SwCADIII\Digital\and 256 224 R0 WINDOW 3 0 0 Invisible 0 SYMATTR Value Vlow=.1 Vhigh={VDD} SYMATTR InstName A1 SYMATTR Value2 Trise=2n Tfall=2n SYMBOL C:\Program\ Files\LTC\SwCADIII\Digital\schmtbuf 160 192 R0 WINDOW 3 8 60 Invisible 0 SYMATTR Value Vt={Vtt} Vh={Vhh} Trise=10n Tfall=10n SYMATTR InstName A2 SYMATTR Value2 Vlow=.1 Vhigh={VDD} Td=193n SYMBOL C:\Program\ Files\LTC\SwCADIII\Digital\schmtbuf 160 256 R0 WINDOW 3 17 89 Invisible 0 SYMATTR Value Vt={Vtt} Vh={Vhh} Trise=10n Tfall=10n SYMATTR InstName A3 SYMATTR Value2 Vlow=.1 Vhigh={VDD} Td=193n ------------------------------------------------ CD4093.asy ------------------------------------------------ Version 4 SymbolType BLOCK LINE Normal 16 -32 -32 -32 LINE Normal 17 32 -32 32 LINE Normal -32 32 -32 -32 LINE Normal 0 -16 16 -16 LINE Normal -8 16 0 -16 LINE Normal -16 16 -8 16 LINE Normal 0 16 -8 16 LINE Normal 8 -16 0 16 CIRCLE Normal 64 8 48 -8 ARC Normal -15 -32 48 32 17 32 16 -32 WINDOW 0 49 -42 Left 0 WINDOW 1 66 28 Left 0 PIN -32 -16 NONE 8 PINATTR PinName a PINATTR SpiceOrder 1 PIN -32 16 NONE 8 PINATTR PinName b PINATTR SpiceOrder 2 PIN 64 0 NONE 8 PINATTR PinName c PINATTR SpiceOrder 3 PIN 0 32 NONE 8 PINATTR PinName gnd PINATTR SpiceOrder 4 ------------------------------------------- and finally an example: Relax.asc ------------------------------------------- Version 4 SHEET 1 900 700 WIRE 80 -80 160 -80 WIRE 160 -80 160 48 WIRE 160 48 112 48 WIRE 16 32 -16 32 WIRE -80 32 -80 96 WIRE 16 64 -16 64 WIRE -16 64 -16 32 WIRE -16 32 -80 32 WIRE -16 32 -16 -80 WIRE -16 -80 0 -80 WIRE -80 192 -80 176 WIRE -80 176 48 176 WIRE -80 176 -80 160 WIRE 48 176 48 80 FLAG -80 192 0 SYMBOL C:\Program\ Files\LTC\SwCADIII\DC4093 48 48 R0 SYMATTR InstName U1 SYMATTR SpiceLine k=3 VDD=5*k Vtt=2.4*k Vhh=.532*k SYMBOL cap -96 96 R0 SYMATTR InstName C1 SYMATTR Value 1n SYMBOL res 96 -96 R90 WINDOW 0 0 56 VBottom 0 WINDOW 3 32 56 VTop 0 SYMATTR InstName R1 SYMATTR Value 20k TEXT -100 216 Left 0 !.tran 1000u ------------------------------------------- ----- Original Message -----
From: <LTspice@...> To: <LTspice@...> Sent: Saturday, February 15, 2003 1:39 AM Subject: [LTspice] Digest Number 23 To unsubscribe from this group, send an email to: LTspice-unsubscribe@... ------------------------------------------------------------------------ There are 4 messages in this issue. Topics in this digest: 1. Some basic uestions From: Massimo Gaspari <gaspari@...> 2. Re: Some basic uestions From: Panama Mike <panamatex@...> 3. New user: how to edit digital models? From: "neel_christian <neel_c@...>" <neel_c@...> 4. Re: New user: how to edit digital models? From: "Helmut Sennewald <helmutsennewald@...>" <helmutsennewald@...> ________________________________________________________________________ ________________________________________________________________________ Message: 1 Date: Fri, 14 Feb 2003 21:41:24 +0100 From: Massimo Gaspari <gaspari@...> Subject: Some basic uestions Hi everybody, I am a new user of LTSpice. Looking into the model list I am not able to find the models for a semiconducor (diffused) resistors and capacitors. They are not very important but some netlists are using them. Are these models available in LTSpice? They are standard models in Berkeley Spice3, may be useful to add them for compatibility. Is there an upper limit for the numeber of components in the standard.* libraries (diode,resistor,capacitor...)? Using the .STEP statement it seems difficult to analyze the different waveforms because it is not possible (is it right?) to understand which value of the parameter is related with a particular waveform. Is there a way to show which value is used with any waveforms? Regards Massimo -- ''~`` ( o o ) +------------------.oooO--(_)--Oooo.------------------+ | | | e-mail: gaspari@... | | | | ICQ # = 166939207 | | | | PGP fingerprint16: | | 76 80 F2 F9 8D 70 F3 D1 42 2B CD 80 29 49 CB 25 | | | | .oooO | | ( ) Oooo. | +---------------------\ (----( )--------------------+ \_) ) / (_/ ________________________________________________________________________ ________________________________________________________________________ Message: 2 Date: Fri, 14 Feb 2003 13:10:50 -0800 (PST) From: Panama Mike <panamatex@...> Subject: Re: Some basic uestions Looking into the model list I am not able to findthe models for a semiconductor (diffused) resistors andYou can use the standard resistor and capacitors model statements. It should be able to understand both Berkeley and PSpice syntax. Is there an upper limit for the number of components(diode,resistor,capacitor...)? Absolutely not, but there isn't any facility there you help you organize your models. If you wish, you can also keep your own libraries separate and include them by putting a SPICE directive on the schematic of the form ".lib <filenamepath>" Using the .STEP statement it seems difficult toYes, it can be difficult. You can navigate an attached cursor from one dataset to the next with the up/down keyboard cursor keys. --Mike __________________________________________________ Do you Yahoo!? Yahoo! Shopping - Send Flowers for Valentine's Day ________________________________________________________________________ ________________________________________________________________________ Message: 3 Date: Fri, 14 Feb 2003 23:25:22 -0000 From: "neel_christian <neel_c@...>" <neel_c@...> Subject: New user: how to edit digital models? Hello Group, I discovered LTSpice a few days ago and I find it very usefull, fun and easy-to-use :-) I am now trying to use mixed-mode simulation, and I cannot edit nor see the models of simple parts like DFLOP (I just want to modify Hold Time, Threshold, etc.). I did it easily for simple analog parts (like nmos,pmos), but no way to find a file (even after a search in the help files and FAQ) for digital parts...maybe I should buy new glasses. A Hint? Thank you in advance for your help Christian Nel ________________________________________________________________________ ________________________________________________________________________ Message: 4 Date: Sat, 15 Feb 2003 00:00:07 -0000 From: "Helmut Sennewald <helmutsennewald@...>" <helmutsennewald@...> Subject: Re: New user: how to edit digital models? --- In LTspice@..., "neel_christian <neel_c@c...>" <neel_c@c...> wrote: Hello Group,fun and easy-to-use :-)Hold Time, Threshold, etc.). I did it easily for simple analog parts(like nmos,pmos), but no way to find a file (even after a search in theHello Christian, new glasses wouldn't help. I had the same question half a year ago. The developer of LTSpice, Mike Engelhardt, kindky send me the necessary information. By the way, he is around here in the group as Panama Mike, but keep it for yourself. It is a secret. The attached sample circuit helps to understand the syntax. This file is also from Mike. Hello Mike, are there even more parameters for digital parts? Best Regards Helmut Original answer from Mike: -------------------------- The low and high levels are given with Vlow and Vhigh. The logic thresholds default to half way between but can be specified with ref. Hysteresis is not possible for gates, but only for the Schmitt devices. Attached is and example that hopefully illustrates. Tripdt is a type of temporal accuracy it should strive for in switching. Sample circuit file "gate.asc": ------------------------------- Version 3 SHEET 1 892 692 WIRE 408 304 408 320 WIRE 420 292 436 292 WIRE 420 300 520 300 WIRE 344 356 344 340 WIRE 344 320 344 296 WIRE 344 296 404 296 WIRE 520 300 520 308 WIRE 520 328 520 340 WIRE 408 244 408 260 WIRE 420 232 436 232 WIRE 404 236 344 236 WIRE 344 236 344 296 WIRE 344 236 344 200 WIRE 344 200 404 200 WIRE 420 200 452 200 WIRE 404 204 404 212 FLAG 408 320 GND FLAG 344 356 GND FLAG 520 340 GND FLAG 408 260 GND FLAG 404 212 GND SYMBOL digital\and 412 280 R0 WINDOW 0 4 6 Left 0 WINDOW 3 4 28 Left 0 WINDOW 39 4 44 Left 0 WINDOW 40 4 52 Left 0 WINDOW 123 4 36 Left 0 SYMATTR InstName A1 SYMATTR Value Vhigh=5 SYMATTR Value2 Vlow=0 Rout=100 SYMATTR SpiceModel AND SYMATTR SpiceLine Ref=2 Td=50n tripdt=3n SYMATTR SpiceLine2 Trise=20n Tfall=40n SYMBOL voltage 344 316 R0 WINDOW 0 6 4 Left 0 WINDOW 3 6 26 Left 0 SYMATTR InstName V1 SYMATTR Value pulse(0 5 0 100n 100n 0 200n) SYMBOL res 516 304 R0 WINDOW 0 9 10 Left 0 WINDOW 3 9 19 Left 0 SYMATTR InstName R1 SYMATTR Value 1K SYMBOL digital\and 412 220 R0 WINDOW 0 4 6 Left 0 WINDOW 3 4 28 Left 0 WINDOW 39 4 44 Left 0 WINDOW 40 4 52 Left 0 WINDOW 123 4 36 Left 0 SYMATTR InstName A2 SYMATTR Value Vhigh=5 SYMATTR Value2 Vlow=0 Rout=100 SYMATTR SpiceModel AND SYMATTR SpiceLine Ref=2 Td=50n tripdt=3n SYMATTR SpiceLine2 Tau=10n SYMBOL digital\schmtbuf 404 184 R0 WINDOW 0 2 8 Left 0 WINDOW 3 5 24 Left 0 WINDOW 123 5 32 Left 0 SYMATTR InstName A3 SYMATTR Value Vt=2.5 Vh=1 SYMATTR Value2 tripdt=3n SYMATTR SpiceModel SCHMITT text 328 368 Left 0 !.tran 1u ________________________________________________________________________ ________________________________________________________________________ Your use of Yahoo! Groups is subject to |
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Re: New user: how to edit digital models?
--- In LTspice@..., "neel_christian <neel_c@c...>"
<neel_c@c...> wrote: --- In LTspice@..., "Helmut Sennewald >is,The attached sample circuit helps to understand the syntax.Thank you very much Helmut, using Mikes's example.Hello Christian, I forgot a very important detail. You have to specify some delay Td for every flipflop. All my simulated counters and flipflops have run as expected only when I specified a delay for every flipflop(e.g. Td=10ns). Your FSM(Finite State Machine) has flipflops and so you have to add this value "Td=xx" to your flipflops. See also the Td parameter in the last gate exmple. Best Regards Helmut |
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Re: New user: how to edit digital models?
--- In LTspice@..., "Helmut Sennewald >
The attached sample circuit helps to understand the syntax.Thank you very much Helmut, In the meantime, I debugged my digital design (a simple FSM) on another mixed-mode simulator (evaluation version of Microcap). Now I'll try to implement it with LTSpice where my main analog design is, using Mikes's example. Probably more feedback at the end of the week-end. Best regards Christian |
Mike Engelhardt
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