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Re: H bridge Series-parallel LLC resonance dc to dc converter

 

The basic LLC converter circuit's output voltage is dependent on the switching frequency around the series impedance of L1 and C1. At frequencies above resonance, L1 dominates in series with the rectified filter current, preventing significant current reversal during a switching interval. Switching can show a ZVS characteristic, if the circulating current is sufficient to charge the switch nodes.

At resonance, a full LC resonant 1/2 period occurs during each capacitive output filter charging cycle. This is a maximum power transfer condition. With output voltage being determined by the load impedance, voltage gain from input to output is possible as this resonance approaches.

A second resonance is possible at lower frequencies, as the shunting L4 comes into effect, however energy transfer occurs in parallel with the inductor, current-limited by C1.

In practical circuits, L1 will appear in series with the load, and will not carry L2 current, in much the way that leakage inductance terms show up in isolation transformers.

The closer the two resonances are to each other the greater assistance the L2 current will provide in enforcing ZVS, however the circulating losses are increased. L2 current does not flow in the load, but will contribute to switch conduction loss.

To study the effect, you're going to have to sweep the frequency down to include the ~87KHz series resonance of the components selected. ZVS effects and switching loss will not be visible if your ideal switches pre-empt it and your rectifiers have no stored charge or stray capacitance in their model.

The impedance of the resonant components must be selected to match the type of source present and the load being served, so that abnormal Q values don't make the circuit hard to control, while delivering the power required.

RL

--- In LTspice@..., "emily_gaopeng" <emily_gaopeng@...> wrote:


hello, everyone, I am doing a simulation about Series-parallel LLC
resonance dc to dc converter. I choose the switching frequency as
100kHZ. In the simulation, the current going through the load is
extremely low. I checked everything, and all the switches and diodes
works fine. I could not figure out why. Any one has done this
simulation before, would you mind giving me some hints?

I have uploaded the file LLC series-parallel resonance dc to dc
converter.asc
<;
97J-kTRY8tqXNLyxTmIYTG2eyTuhOlB50Tjr078hdg9epkiTBpTmkx8j3-/%20Examples/A&#92;
pps/LLC%20series-parallel%20resonance%20dc%20to%20dc%20converter.asc>
in
<>

Thank you so much
Re: Some confusion about pass-transistor circuit

Jim Wagner
 

On Sep 24, 2011, at 5:36 PM, teslastrike wrote:

Thanks i tried it worked, however....

What if i want to simulate now some reasonable logic, which changes
FAST. And in that case this 1uf capacitor i placed basically kills
the whole timing...

but yes, as you mentioned when i decrease capacitance i get again
3.3v on first stage...

So.. if i want to simulate some small circuit which is lets say part
of some chip where capacitances are measured in femtoFarads...its
not going to work then.

You are asking VERY much for any circuit. consider a 1uf capacitor
charged to 3.3V in 10ns. The relationship is Q = CV or I = C dV/dT. If
the current is constant for the entire charging time, then take dV =
3.3V, dT = 10ns and C = 1uF.

Then you must have I = 100 * 3.3 Amperes or 330Amperes. Any other
strategy (than constant current for the full charging time) will have
even higher currents at some point in charging cycle. The simple fact
is that charging such a large capacitor in such a short time is not
practical with "ordinary" circuits.

Jim Wagner



[Non-text portions of this message have been removed]
Re: Some confusion about pass-transistor circuit

Ganesan
 

Also you don't expect pass transistor logic to hold stuff for
milliseconds on femto farad capacitors!! Try microseconds or nanoseconds..
Cheers
AG

On 9/24/2011 7:36 PM, teslastrike wrote:

Thanks i tried it worked, however....

What if i want to simulate now some reasonable logic, which changes
FAST. And in that case this 1uf capacitor i placed basically kills the
whole timing...

but yes, as you mentioned when i decrease capacitance i get again 3.3v
on first stage...

So.. if i want to simulate some small circuit which is lets say part
of some chip where capacitances are measured in femtoFarads...its not
going to work then.
Re: Some confusion about pass-transistor circuit

 

ok i was totally wrong now.

in case if i want to simulate some on chip stuff, i need completely new and different model with appropriate values.

here im using just already made package which already has predetermined transistors.

ok.
Re: Some confusion about pass-transistor circuit

 

Thanks i tried it worked, however....

What if i want to simulate now some reasonable logic, which changes FAST. And in that case this 1uf capacitor i placed basically kills the whole timing...

but yes, as you mentioned when i decrease capacitance i get again 3.3v on first stage...

So.. if i want to simulate some small circuit which is lets say part of some chip where capacitances are measured in femtoFarads...its not going to work then.
Re: Some confusion about pass-transistor circuit

Ganesan
 

In the real world, people seldom use resistive loads with pass
transistor logic Capacitive loads is more common..
So I would put capacitive loads and run .tran with the uic option..
cheers
AG

On 9/24/2011 7:04 PM, teslastrike wrote:

I have updated pass_transistor1.asc in Temp,

Now i added small stair circuit to the right,

Vdd=3.3v, Vtn=1.1v
So the expected voltages are:

Va = Vdd-Vtn = 2.2v
Vb = Vdd - 2Vtn = 1.1v
Vc = Vdd - 3Vtn = 0v
Re: Some confusion about pass-transistor circuit

 

I have updated pass_transistor1.asc in Temp,

Now i added small stair circuit to the right,

Vdd=3.3v, Vtn=1.1v
So the expected voltages are:

Va = Vdd-Vtn = 2.2v
Vb = Vdd - 2Vtn = 1.1v
Vc = Vdd - 3Vtn = 0v
Re: Some confusion about pass-transistor circuit

 

Helmut,

I was talking about pass transistor logic. Im now studying it, i took a look at the page you showed, it kind of explains it in more complicated way.

Im thinking of it in a straightforward way:

nMOS transistor is good at passing logic LOW when turned on, so if drain is LOW the source will be strong LOW. But it is bad at passing logic HIGH when turned on, so when drain is HIGH the source will be Vdd - Vtn, or weak HIGH.

Reason: When you want to pass HIGH, you put Vdd on drain, but you will NOT be able to get same Vdd on source, because if it would be the case then Vds would be zero, and transistor would be cutoff.

The maximum allowed value which you will be able to get on the source is Vdd - Vtn (and then Vds = Vdd - (Vdd-Vtn) = Vtn) to satisfy the condition to have the transistor ON.

That is why, you technically are passing WEAK HIGH.


same concept applies to pMOS, except that there you dont get ideal LOW (or strong low) you get weak low, which is Vtp.


So, i just wanted to play around with different combinations in LTspice, and the suggestion to add huge resistance between output and ground solved the problem!

Thanks everyone for discussion.
Re: ltspdisto howto?

Tony Casey
 

--- In LTspice@..., "bikercalvin" <BikerCalvin@...> wrote:

Hi,

have to have a closer look at audio analyser. At least the example did run from the start. It showed Distortion over O/P level, which is without doubt a useful feature. But I was looking for the ltspdisto-feature ?Distortion over frequency?.
Hello Calvin,

The analyser can easily be set to run vs. frequency or amplitude.

In the top line, which annotated: "Change your amplitudes and frequencies here", swap the positions of the loops stepping VInrms and Freq, i.e.
Was: .step dec param VInrms 10m 1 6 ;param Freq list 1k 5k 15k
to: .step dec param Freq 20 20k 3; dec param VInrms 10m 1 6

(The .step loop following the semi-colon is disabled; it was left to illustrate how to swap the sweep mode, but was obviously not clear enough.)

You can also stop the load from being stepped in the second loop:
Was: .step param Rl list 4 8
to: .param Rl 8

.. if you don't require that feature.

If you sweep frequency, instead of amplitude, you will need to change the x-axis variable in the display:
Click the x-axis and use "frequency" instead of "VInrms" as the plot variable. I have upload a screenshot and a replacement .plt file for use with swept frequency.

Please note: the analysis is quite slow at low frequencies - this is normal. Should be adequately fast at 1k or higher.

If you have any further questions, please ask.

Regards,
Tony
Re: Some confusion about pass-transistor circuit

Ganesan
 

By the way don't name Ground as VSS.. The netlister corrected it.
There is no such thing as an off switch.. Even SW defaults to 1/Gmin for
its ROFF
My file is in
Files ->Temp
ag_sw.asc
<>

Cheers
AG

On 9/24/2011 5:36 PM, Ganesan wrote:

I am sorry it was 11e5 and not 1E5...

On 9/24/2011 5:33 PM, Ganesan wrote:

I put a 1uf capacitor on node Vb....I get 3.33V when I run ,tran
without UIC and 2.2v when I run it with .UIC.
When I change the load cap to 1pf, both answers are 3.3v
When I go back to the 1uf capacitor and run it for 1e5seconds (that is
right) it does go to 3.3 volts.. (even with UIC)
It says that the MOS transistor or the associated diode leaks a bit....
I am sure a behavioral switch with its threshold set right will behave
differently..
Cheers
AG

On 9/24/2011 5:10 PM, Rick wrote:



--- In LTspice@... <mailto:LTspice%40yahoogroups.com>
<mailto:LTspice%40yahoogroups.com>
<mailto:LTspice%40yahoogroups.com>,
"teslastrike" <teslastrike@...> wrote:

Hello, as we know nMOS transistors are good at passing logic 0
(logic high will be degraded by Vtn), and pMOS transistors are good at
passing logic 1 (logic zero will be degraded and equal to |Vtp|)

Now i have constructed a simple circuit with pMOS and nMOS in
series, both are turned on, the signal coming to pMOS is HIGH, so
between these transistors the voltage Va should be equal almost to
Vdd, now Va is a HIGH voltage and is passed to output Vb, but Vb
should be equal to Va - Vtn (which is for nMOS which i used is 1.1v),
so i expect Vb be equal to about 3.3-1.1 = 2.2v

However, interesting thing is that when i simulate almost two
voltages are same, and Vb is even higher than Va...which kind of does
not make much sense, unless im missing something?

i have attached pass_transistor1.asc in Temp folder to take a
look at.

thanks.
Teslastrike,

Put a load resistor on the output and the results will be reasonable.
Actually, the result you are getting with an open circuit is not
unreasonable, considering that you have used the default settings and
the "error" is only 2E-4 percent.

Rick
Re: Some confusion about pass-transistor circuit

Ganesan
 

I am sorry it was 11e5 and not 1E5...

On 9/24/2011 5:33 PM, Ganesan wrote:

I put a 1uf capacitor on node Vb....I get 3.33V when I run ,tran
without UIC and 2.2v when I run it with .UIC.
When I change the load cap to 1pf, both answers are 3.3v
When I go back to the 1uf capacitor and run it for 1e5seconds (that is
right) it does go to 3.3 volts.. (even with UIC)
It says that the MOS transistor or the associated diode leaks a bit....
I am sure a behavioral switch with its threshold set right will behave
differently..
Cheers
AG

On 9/24/2011 5:10 PM, Rick wrote:



--- In LTspice@... <mailto:LTspice%40yahoogroups.com>
<mailto:LTspice%40yahoogroups.com>,
"teslastrike" <teslastrike@...> wrote:

Hello, as we know nMOS transistors are good at passing logic 0
(logic high will be degraded by Vtn), and pMOS transistors are good at
passing logic 1 (logic zero will be degraded and equal to |Vtp|)

Now i have constructed a simple circuit with pMOS and nMOS in
series, both are turned on, the signal coming to pMOS is HIGH, so
between these transistors the voltage Va should be equal almost to
Vdd, now Va is a HIGH voltage and is passed to output Vb, but Vb
should be equal to Va - Vtn (which is for nMOS which i used is 1.1v),
so i expect Vb be equal to about 3.3-1.1 = 2.2v

However, interesting thing is that when i simulate almost two
voltages are same, and Vb is even higher than Va...which kind of does
not make much sense, unless im missing something?

i have attached pass_transistor1.asc in Temp folder to take a look at.

thanks.
Teslastrike,

Put a load resistor on the output and the results will be reasonable.
Actually, the result you are getting with an open circuit is not
unreasonable, considering that you have used the default settings and
the "error" is only 2E-4 percent.

Rick
Re: Some confusion about pass-transistor circuit

Ganesan
 

I put a 1uf capacitor on node Vb....I get 3.33V when I run ,tran
without UIC and 2.2v when I run it with .UIC.
When I change the load cap to 1pf, both answers are 3.3v
When I go back to the 1uf capacitor and run it for 1e5seconds (that is
right) it does go to 3.3 volts.. (even with UIC)
It says that the MOS transistor or the associated diode leaks a bit....
I am sure a behavioral switch with its threshold set right will behave
differently..
Cheers
AG

On 9/24/2011 5:10 PM, Rick wrote:



--- In LTspice@... <mailto:LTspice%40yahoogroups.com>,
"teslastrike" <teslastrike@...> wrote:

Hello, as we know nMOS transistors are good at passing logic 0
(logic high will be degraded by Vtn), and pMOS transistors are good at
passing logic 1 (logic zero will be degraded and equal to |Vtp|)

Now i have constructed a simple circuit with pMOS and nMOS in
series, both are turned on, the signal coming to pMOS is HIGH, so
between these transistors the voltage Va should be equal almost to
Vdd, now Va is a HIGH voltage and is passed to output Vb, but Vb
should be equal to Va - Vtn (which is for nMOS which i used is 1.1v),
so i expect Vb be equal to about 3.3-1.1 = 2.2v

However, interesting thing is that when i simulate almost two
voltages are same, and Vb is even higher than Va...which kind of does
not make much sense, unless im missing something?

i have attached pass_transistor1.asc in Temp folder to take a look at.

thanks.
Teslastrike,

Put a load resistor on the output and the results will be reasonable.
Actually, the result you are getting with an open circuit is not
unreasonable, considering that you have used the default settings and
the "error" is only 2E-4 percent.

Rick
Re: Some confusion about pass-transistor circuit

 

--- In LTspice@..., "teslastrike" <teslastrike@...> wrote:

Hello, as we know nMOS transistors are good at passing logic 0 (logic high will be degraded by Vtn), and pMOS transistors are good at passing logic 1 (logic zero will be degraded and equal to |Vtp|)

Now i have constructed a simple circuit with pMOS and nMOS in series, both are turned on, the signal coming to pMOS is HIGH, so between these transistors the voltage Va should be equal almost to Vdd, now Va is a HIGH voltage and is passed to output Vb, but Vb should be equal to Va - Vtn (which is for nMOS which i used is 1.1v), so i expect Vb be equal to about 3.3-1.1 = 2.2v

However, interesting thing is that when i simulate almost two voltages are same, and Vb is even higher than Va...which kind of does not make much sense, unless im missing something?

i have attached pass_transistor1.asc in Temp folder to take a look at.

thanks.
Hello teslastrike,

Are you talking about the transfer-gate or about pass
transistor logic?

I knew transfer gates, but pass transistor logic in general
has been new for me.



Best regards,
Helmut
Re: Some confusion about pass-transistor circuit

Jim Wagner
 

On Sep 24, 2011, at 3:13 PM, Andy wrote:

Hello, as we know nMOS transistors are good at passing logic 0
(logic high will be degraded by Vtn), and pMOS transistors are good
at passing logic 1 (logic zero will be degraded and equal to |Vtp|)
The normal way to lessen that problem is to put an N and P MOS
transistor in parallel with one another.

Now i have constructed a simple circuit with pMOS and nMOS in
series,

Why series?

However, interesting thing is that when i simulate almost two
voltages
are same, and Vb is even higher than Va...which kind of does not
make
much sense, unless im missing something?
The circuit has absolutely no resistance to ground. Nice but not
realistic.

Add a 1 Meg resistor or even a 1 Gig resistor from Vb to ground and
see the effect it has.

The NMOS transistor won't drop the voltage if it has zero current
through its channel.

Also, I am not positive but I suspect the substrate pin connections on
your transistors might not be realistic.

Andy
Series is the usual connection used in CMOS gate output structures.

Jim Wagner
Oregon Research Electronics

[Non-text portions of this message have been removed]
Re: Some confusion about pass-transistor circuit

 

Hello, as we know nMOS transistors are good at passing logic 0
(logic high will be degraded by Vtn), and pMOS transistors are good
at passing logic 1 (logic zero will be degraded and equal to |Vtp|)
The normal way to lessen that problem is to put an N and P MOS
transistor in parallel with one another.

Now i have constructed a simple circuit with pMOS and nMOS in series,
Why series?

However, interesting thing is that when i simulate almost two voltages
are same, and Vb is even higher than Va...which kind of does not make
much sense, unless im missing something?
The circuit has absolutely no resistance to ground. Nice but not realistic.

Add a 1 Meg resistor or even a 1 Gig resistor from Vb to ground and
see the effect it has.

The NMOS transistor won't drop the voltage if it has zero current
through its channel.

Also, I am not positive but I suspect the substrate pin connections on
your transistors might not be realistic.

Andy
Re: Some confusion about pass-transistor circuit

 

--- In LTspice@..., "teslastrike" <teslastrike@...> wrote:

Hello, as we know nMOS transistors are good at passing logic 0 (logic high will be degraded by Vtn), and pMOS transistors are good at passing logic 1 (logic zero will be degraded and equal to |Vtp|)

Now i have constructed a simple circuit with pMOS and nMOS in series, both are turned on, the signal coming to pMOS is HIGH, so between these transistors the voltage Va should be equal almost to Vdd, now Va is a HIGH voltage and is passed to output Vb, but Vb should be equal to Va - Vtn (which is for nMOS which i used is 1.1v), so i expect Vb be equal to about 3.3-1.1 = 2.2v

However, interesting thing is that when i simulate almost two voltages are same, and Vb is even higher than Va...which kind of does not make much sense, unless im missing something?

i have attached pass_transistor1.asc in Temp folder to take a look at.

thanks.
Teslastrike,

Put a load resistor on the output and the results will be reasonable. Actually, the result you are getting with an open circuit is not unreasonable, considering that you have used the default settings and the "error" is only 2E-4 percent.

Rick
Re: Inductor initial conditions

Ganesan
 

Thanks Helmut.. I noticed when the .IC with . V(10) is used, for the
first time point it is ignored and then included with a very sharp rise
time.. You have to zoom in real carefully to observe it..
I think LTspice confuses between t= 0minus and t= 0 plus and t=
infinity which most text books define as dc..
I dont have a problem living witht the quirks and idiosyncrasies of
LTspice because

a) it is free
b) its advantages are many many
and
c) there is a great user community which is willing to give a helping
hand (helmut, tony, rick, john, to name a few)

My quibble is that these exceptional behaviors be clearly documented (
perhaps as another link in FIles such as LTspice_peculiarities)
Right now it seems to be carried in the heads of a few and an awful
amount of designer time and "bandwidth" is wasted chasing these..
No useful living tool can be perfect.. But a clear documentation of its
limitations will make it easier to live with.(Small timesteps when
making frequency measurements even if it is a resistive circuit;. dc is
not what you think it is; the distinction between a flop and a latch;
time domain analysis of Laplace sources; the conditional use of .IC ,
to name a few)
Thanks for your time attention and care and the extraordinary diligence
of this group.. Thanks everybody.
Cheers
AG

On 9/24/2011 3:12 PM, Helmut wrote:



--- In LTspice@... <mailto:LTspice%40yahoogroups.com>,
"Apparajan" <dg1@...> wrote:

Below is a simple netlist.
* C:&#92;Documents and Settings&#92;ganesan&#92;My Documents&#92;Downloads&#92;Draft1.asc
R1 out 0 1
L2 out 0 1
.ic I(L2) =1.0
.tran 5 uic
.backanno
.end
I expect the output to be -1v with a time constant of 1 sec.
LTspice says otherwise..
What am I doing stupid?
cheers
AG
Hello AG,

Let's assume we have a capacitor between node 10 and 0 and a
inductor L1.

.tran 10m uic
.ic V(10)=1 --> used
.ic I(L1)=1 --> will be ignored
PSPICE has used here .ic I(L1) too.

.tran 10m
.ic V(10)=1 --> used
.ic I(L1)=1 --> used

I have discussed this case with Mike in the last few hours.
Mike told me that the behavior of LTspice is as intended,

Best regards,
Helmut
Some confusion about pass-transistor circuit

 

Hello, as we know nMOS transistors are good at passing logic 0 (logic high will be degraded by Vtn), and pMOS transistors are good at passing logic 1 (logic zero will be degraded and equal to |Vtp|)

Now i have constructed a simple circuit with pMOS and nMOS in series, both are turned on, the signal coming to pMOS is HIGH, so between these transistors the voltage Va should be equal almost to Vdd, now Va is a HIGH voltage and is passed to output Vb, but Vb should be equal to Va - Vtn (which is for nMOS which i used is 1.1v), so i expect Vb be equal to about 3.3-1.1 = 2.2v

However, interesting thing is that when i simulate almost two voltages are same, and Vb is even higher than Va...which kind of does not make much sense, unless im missing something?

i have attached pass_transistor1.asc in Temp folder to take a look at.

thanks.
Re: H bridge Series-parallel LLC resonance dc to dc converter

 

I was looking at emily's file and noticed the current in series components, C1 and L1 are OK at the beginning but not for the thousands of Amp spikes in C1. I am guessing that this may be an ill conditioned simulation somehow, so is that why the currents in these series components different ??

boB

--- In LTspice@..., "Rick" <sawreyrw@...> wrote:



--- In LTspice@..., "emily_gaopeng" <emily_gaopeng@> wrote:


hello, everyone, I am doing a simulation about Series-parallel LLC
resonance dc to dc converter. I choose the switching frequency as
100kHZ. In the simulation, the current going through the load is
extremely low. I checked everything, and all the switches and diodes
works fine. I could not figure out why. Any one has done this
simulation before, would you mind giving me some hints?

I have uploaded the file LLC series-parallel resonance dc to dc
converter.asc

Thank you so much
Emily,

This is off topic, but I'll give you a couple of hints anyway.

1. Since each side of the bridge is on exactly half the time the average voltage from point A to B is zero. This is why the output is essentially zero.

2. Your bridge is OK, but you should really have a small dead time for each switching event, and the duty cycle should not be 50%. Without the dead time you may get huge shoot through currents; take a look at the currents through the switches. You need separate drive signals for each pair of switches.

3. I'm not too familiar with this particular circuit, but I don't think it is suited for a full bridge. I could be wrong.

4. Helmut already told you the frequency is 100 MHz, not 100 KHz.

Rick
Re: Inductor initial conditions

 

--- In LTspice@..., "Helmut" <helmutsennewald@...> wrote:



--- In LTspice@..., "Apparajan" <dg1@> wrote:

Below is a simple netlist.
* C:&#92;Documents and Settings&#92;ganesan&#92;My Documents&#92;Downloads&#92;Draft1.asc
R1 out 0 1
L2 out 0 1
.ic I(L2) =1.0
.tran 5 uic
.backanno
.end
I expect the output to be -1v with a time constant of 1 sec.
LTspice says otherwise..
What am I doing stupid?
cheers
AG

Hello AG,

Let's assume we have a capacitor between node 10 and 0 and a
inductor L1.

.tran 10m uic
.ic V(10)=1 --> used
.ic I(L1)=1 --> will be ignored
PSPICE has used here .ic I(L1) too.


.tran 10m
.ic V(10)=1 --> used
.ic I(L1)=1 --> used


I have discussed this case with Mike in the last few hours.
Mike told me that the behavior of LTspice is as intended,

Best regards,
Helmut
Hello again,

I forgot to mention that Mike recommended to use IC=1 in the
inductor for this case.

.tran 10m uic

L1 20 0 1m IC=1


Best regards,
Helmut
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