¿ªÔÆÌåÓý

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Classic Menu vs Keyboard shortcuts

 

Hi All
?
How can one restore the Classic Menu in LTSpice Version 24.1.6?
?
Regards
ik
Re: "Flaw" in UniversalOpamps

 

On Wed, Apr 9, 2025 at 10:42 AM, <gkhebert2@...> wrote:
...? The model designer(s) of the universal opamp seem to have assumed that all opamps have MOS inputs ...
That might be so, but I personally doubt it.? Just my opinion.

...? Opamps with bipolar input devices have substantially lower differential input impedance than common-mode input impedance ...
That might be why these UniversalOpamp models lack any explicit provision for Rin(CM).? It seems to have been ignored - even though its presence is definitely there in these models, even disproportionately there.
?
...? The also have input bias currents, which are missing from all of the universal opamp models.
That might have been intentional, to give you just the basics of a "universal" op-amp without that particular distraction.? Some bipolar op-amps have input bias cancellation, with an average bias current of zero and a spread around it, both positive and negative.? That makes it difficult to represent in a SPICE model.
?
At the time these UniversalOpamp models were made, which I believe would have been 20 or 25+ years ago, bipolars were the first choice.
?
Andy
?
Re: "Flaw" in UniversalOpamps

 

On Wed, Apr 9, 2025 at 11:09 AM, John Woodgate wrote:

Weren't these models changed soon after AD took over?

Yes and no.
?
They were re-packaged with altered symbol and model names.? But as far as I know, the innards of each of the models themselves were unchanged by ADI.
?
Andy
?
Re: "Flaw" in UniversalOpamps

 

¿ªÔÆÌåÓý

Weren't these models changed soon after AD took over?

On 2025-04-09 16:04, Andy I via groups.io wrote:
It seems as if whoever designed these Universal Opamps gave no thought whatsoever to a common-mode input impedance.? Not one of them has a parameter for that.
?
If you ground either input pin and measure the impedance between the input pins, you get what appears to be an impedance between the pins of Rin, so you can fool yourself by doing that.
?
I assumed it was Mike Engelhardt who made these models.? I am guessing he just overlooked this.
?
Andy
?
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion

Virus-free.
Re: "Flaw" in UniversalOpamps

 

It seems as if whoever designed these Universal Opamps gave no thought whatsoever to a common-mode input impedance.? Not one of them has a parameter for that.
?
If you ground either input pin and measure the impedance between the input pins, you get what appears to be an impedance between the pins of Rin, so you can fool yourself by doing that.
?
I assumed it was Mike Engelhardt who made these models.? I am guessing he just overlooked this.
?
Andy
?
Re: "Flaw" in UniversalOpamps

 

¿ªÔÆÌåÓý

Far from 'universal', then. These surprising issues should be fixed, because the errors caused by the present models could be very serious. Input resistances are often very important in opamp circuits. It's possible to work round the absence of bias currents, and it's probably better to do that than include them in the models.

On 2025-04-09 15:36, gkhebert2 via groups.io wrote:
I also noticed the input impedance issue some time ago.? The model designer(s) of the universal opamp seem to have assumed that all opamps have MOS inputs wherein the input resistance is determined almost entirely by the impedance of the ESD protection structures to the supply rails.? Opamps with bipolar input devices have substantially lower differential input impedance than common-mode input impedance and this does manifest as performance differences in different circuit topologies.? The also have input bias currents, which are missing from all of the universal opamp models.
--
Best wishes John Woodgate RAYLEIGH Essex OOO-Own Opinions Only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion

Virus-free.
Re: "Flaw" in UniversalOpamps

 

I also noticed the input impedance issue some time ago.? The model designer(s) of the universal opamp seem to have assumed that all opamps have MOS inputs wherein the input resistance is determined almost entirely by the impedance of the ESD protection structures to the supply rails.? Opamps with bipolar input devices have substantially lower differential input impedance than common-mode input impedance and this does manifest as performance differences in different circuit topologies.? The also have input bias currents, which are missing from all of the universal opamp models.
Re: "Flaw" in UniversalOpamps

 

Definitely my fault. For the confusing.
Too much cross references.?
?
Regretting..
Re: "Flaw" in UniversalOpamps

 

In two versions , LTspice XVII & V.24,?
?
The lib file 'ADI1.lib' has a little difference, in XVII there is one line extra added that caused the error, this line doesn't exist in V.24.
Thus, if in LTspice V.24 (has default lib in different folder path) that added extra lib path, eg: from LTspice XVII, error may happens.
?
.ends ADA4830*TEST3 Macro-model.ends ADA4830*TEST3 Macro-model
?
For your reference.
?
Best regards.
Re: "Flaw" in UniversalOpamps

 

Hi, :
?
I must say sorry, the problem doesn't exist.
I just tried in another platform, with XVII & V.24, ran the same file using 'AD746', it runs well.
?
I guess, it's because the search paths configuration in V24. I pasted lots paths from XVII's lib paths (including recursive) into V.24's 'searh paths' setting which doesn't support recursive searching.
Then it gives the wrong reference to ...something else. (ADA4830? ADA4857? ...)
?
The previous was a misleading.
?
Thank you very much.
Best regards.
Re: "Flaw" in UniversalOpamps

 

Hi, :
?
The UniversalOpamp model really makes sense, it draws lots current flow.
Since it hurts because of the larger power dissipation, so I give a shot by using local 'AD746', it draws much fewer current, though possibly could be adjusted by external parameters, more efforts needed.
Above ~2.29Hz, the common mode impedance will be larger than differential mode impedance about starting with 9.8G. (Same as gravity value) Apply the common sense rule, common mode impedance should be greater than differential mode.
?
Maybe I don't have the common sense, knowing so much different things all over the world, eg: I haven't noticed the 'common mode > differential mode... things'. But still eager to learn more.
Maybe something is inevitable ,eg: Unfortunately, we can't know/fix every bug, same as the laplace transformation issue mentioned before, see below: That one broken my heart, (sorry correct to ) religion.
?
All models should play happily, but the simulator platform mechanism always alternate between bright & dark, peak & valley. Sooner or later, unfortunately.
Which , I mean in the file I changed from the UniversalOpamps to AD746, it plays very sadly not going right in new simulator LTspice V.24.1.5 , which I modified it in LTspice XVII V.17.0.37.0, and when migrate it to run in new one , it feedbacks the following message:
?
"
syntax error
.ends ADA4830*TEST3###> Macro-model
*Function:Amplifier
*
*Revision History:
*Rev.2.1 Nov 2016-JL
*Power Down Function Updated - 11/21/2016 (JL)
*Copyright 2016 by Analog Devices
*
*Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spicemodels/license
*for License Statement. Use of this model indicates your acceptance
*of the terms and provisions in the License Staement.
*
*Tested on MultSIm, SiMetrix(NGSpice), PSpice
*
*Not modeled: Distortion, PSRR, Overload Recovery,
* ? ? ? ? ? ? Shutdown Turn On/Turn Off time, CMRR
*
*Parameters modeled include:
* ? Vos, Ibias, Input CM limits and Typ output voltge swing over full supply range,
* ? Open Loop Gain & Phase, Slew Rate, Output current limits, Voltage & Current Noise over temp,
* ? Capacitive load drive, Quiescent and dynamic supply currents,
* ? Shut Down pin functionality where applicable,
* ? Single supply & offset supply functionality.
*
*Removed FB pin for LTSPICE (temporary)
*
*Node Assignments
* ? ? ? ? ? ? ?Non-Inverting Input
* ? ? ? ? ? ? ?| ? Inverting Input
* ? ? ? ? ? ? ?| ? | ? Positive supply
* ? ? ? ? ? ? ?| ? | ? | ? Negative supply
* ? ? ? ? ? ? ?| ? | ? | ? | ? Output
* ? ? ? ? ? ? ?| ? | ? | ? | ? |
* ? ? ? ? ? ? ?| ? | ? | ? | ? | ? ?PD
* ? ? ? ? ? ? ?| ? | ? | ? | ? | ? ?|
.Subckt ADA4857 100 101 102 103 104 106
*
***Power Supplies***
Rz1 ? ?102 ? ?1020 ? ?Rideal ? ?1e-6
Rz2 ? ?103 ? ?1030 ? ?Rideal ? ?1e-6
Ibias ? ?1020 ? ?1030 ? ?dc ? ?0.35e-3
DzPS ? ?98 ? ?1020 ? ?diode
Iquies ? ?1020 ? ?98 ? ?dc ? ?4.65e-3
S1 ? ?98 ? ?1030 ? ?113 ? ?106 ? ?Switch
R1 ? ?1020 ? ?99 ? ?Rideal ? ?1e7
R2 ? ?99 ? ?1030 ? ?Rideal ? ?1e7
e1 ? ?111 ? ?110 ? ?1020 ? ?110 ? ?1
e2 ? ?110 ? ?112 ? ?110 ? ?1030 ? ?1
e3 ? ?110 ? ?0 ? ?99 ? ?0 ? ?1
*
*
***Inputs***
S2 ? ?1 ? ?100 ? ?113 ? ?106 ? ?Switch
S3 ? ?9 ? ?101 ? ?113 ? ?106 ? ?Switch
VOS ? ?1 ? ?2 ? ?dc ? ?2e-3
IbiasP ? ?110 ? ?2 ? ?dc ? ?-2e-6
IbiasN ? ?110 ? ?9 ? ?dc ? ?-2e-6
RinCMP ? ?110 ? ?2 ? ?Rideal ? ?8e6
RinCMN ? ?9 ? ?110 ? ?Rideal ? ?8e6
CinCMP ? ?110 ? ?2 ? ?0.4e-12
CinCMN ? ?9 ? ?110 ? ?0.4e-12
IOS ? ?9 ? ?2 ? ?0.05e-6
RinDiff ? ?9 ? ?2 ? ?Rideal ? ?4000e3
CinDiff ? ?9 ? ?2 ? ?0.25e-12
*
*
***Non-Inverting Input with Clamp***
g1 ? ?3 ? ?110 ? ?110 ? ?2 ? ?0.001
RInP ? ?3 ? ?110 ? ?Rideal ? ?1e3
RX1 ? ?40 ? ?3 ? ?Rideal ? ?0.001
DInP ? ?40 ? ?41 ? ?diode
DInN ? ?42 ? ?40 ? ?diode
VinP ? ?111 ? ?41 ? ?dc ? ?1.46
VinN ? ?42 ? ?112 ? ?dc ? ?1.46
*
*
***Vnoise***
hVn ? ?6 ? ?5 ? ?Vmeas1 ? ?707.10678
Vmeas1 ? ?20 ? ?110 ? ?DC ? ?0
Vvn ? ?21 ? ?110 ? ?dc ? ?0.65
Dvn ? ?21 ? ?20 ? ?DVnoisy
hVn1 ? ?6 ? ?7 ? ?Vmeas2 ? ?707.10678
Vmeas2 ? ?22 ? ?110 ? ?dc ? ?0
Vvn1 ? ?23 ? ?110 ? ?dc ? ?0.65
Dvn1 ? ?23 ? ?22 ? ?DVnoisy
*
*
***Inoise***
FnIN ? ?9 ? ?110 ? ?Vmeas3 ? ?0.7071068
Vmeas3 ? ?51 ? ?110 ? ?dc ? ?0
VnIN ? ?50 ? ?110 ? ?dc ? ?0.65
DnIN ? ?50 ? ?51 ? ?DINnoisy
FnIN1 ? ?110 ? ?9 ? ?Vmeas4 ? ?0.7071068
Vmeas4 ? ?53 ? ?110 ? ?dc ? ?0
VnIN1 ? ?52 ? ?110 ? ?dc ? ?0.65
DnIN1 ? ?52 ? ?53 ? ?DINnoisy
*
FnIP ? ?2 ? ?110 ? ?Vmeas5 ? ?0.7071068
Vmeas5 ? ?31 ? ?110 ? ?dc ? ?0
VnIP ? ?30 ? ?110 ? ?dc ? ?0.65
DnIP ? ?30 ? ?31 ? ?DIPnoisy
FnIP1 ? ?110 ? ?2 ? ?Vmeas6 ? ?0.7071068
Vmeas6 ? ?33 ? ?110 ? ?dc ? ?0
VnIP1 ? ?32 ? ?110 ? ?dc ? ?0.65
DnIP1 ? ?32 ? ?33 ? ?DIPnoisy
*
*
***CMRR***
RcmrrP ? ?3 ? ?10 ? ?Rideal ? ?1e12
RcmrrN ? ?10 ? ?9 ? ?Rideal ? ?1e12
g10 ? ?11 ? ?110 ? ?10 ? ?110 ? ?-1e-10
Lcmrr ? ?11 ? ?12 ? ?1e-12
Rcmrr ? ?12 ? ?110 ? ?Rideal ? ?1e3
e4 ? ?5 ? ?3 ? ?11 ? ?110 ? ?1
*
*
***Power Down***
VPD ? ?111 ? ?80 ? ?dc ? ?2
VPD1 ? ?81 ? ?0 ? ?dc ? ?2.2
RPD ? ?111 ? ?106 ? ?Rideal ? ?0.2e6
ePD ? ?80 ? ?113 ? ?82 ? ?0 ? ?1
RDP1 ? ?82 ? ?0 ? ?Rideal ? ?1e3
CPD ? ?82 ? ?0 ? ?1e-10
S5 ? ?81 ? ?82 ? ?83 ? ?113 ? ?Switch
CDP1 ? ?83 ? ?0 ? ?1e-12
RPD2 ? ?106 ? ?83 ? ?1e6
*
*
***Feedback Pin***
RF ? ?105 ? ?104 ? ?Rideal ? ?0.001
*
*
***VFB Stage***
g200 ? ?200 ? ?110 ? ?7 ? ?9 ? ?1
R200 ? ?200 ? ?110 ? ?Rideal ? ?250
DzSlewP ? ?201 ? ?200 ? ?DzSlewP
DzSlewN ? ?201 ? ?110 ? ?DzSlewN
*
*
***Dominant Pole at 613 Hz***
g210 ? ?210 ? ?110 ? ?200 ? ?110 ? ?10.9069e-6
R210 ? ?210 ? ?110 ? ?Rideal ? ?0.26e6
C210 ? ?210 ? ?110 ? ?1e-012
*
*
***Output Voltage Clamp-1***
RX2 ? ?60 ? ?210 ? ?Rideal ? ?0.001
DzVoutP ? ?61 ? ?60 ? ?DzVoutP
DzVoutN ? ?60 ? ?62 ? ?DzVoutN
DVoutP ? ?61 ? ?63 ? ?diode
DVoutN ? ?64 ? ?62 ? ?diode
VoutP ? ?65 ? ?63 ? ?dc ? ?6.567
VoutN ? ?64 ? ?66 ? ?dc ? ?6.567
e60 ? ?65 ? ?110 ? ?111 ? ?110 ? ?1.209
e61 ? ?66 ? ?110 ? ?112 ? ?110 ? ?1.209
*
*
***Pole at 810MHz***
g220 ? ?220 ? ?110 ? ?210 ? ?110 ? ?0.001
R220 ? ?220 ? ?110 ? ?Rideal ? ?1000
C220 ? ?220 ? ?110 ? ?0.1965e-12
*
***Pole at 12200MHz***
g230 ? ?230 ? ?110 ? ?220 ? ?110 ? ?0.001
R230 ? ?230 ? ?110 ? ?Rideal ? ?1000
C230 ? ?230 ? ?110 ? ?0.013e-12
*
***Buffer***
g240 ? ?240 ? ?110 ? ?230 ? ?110 ? ?0.001
R240 ? ?240 ? ?110 ? ?Rideal ? ?1000
*
***Buffer***
g245 ? ?245 ? ?110 ? ?240 ? ?110 ? ?0.001
R245 ? ?245 ? ?110 ? ?Rideal ? ?1000
*
***Buffer***
g250 ? ?250 ? ?110 ? ?245 ? ?110 ? ?0.001
R250 ? ?250 ? ?110 ? ?Rideal ? ?1000
*
***Buffer***
g255 ? ?255 ? ?110 ? ?250 ? ?110 ? ?0.001
R255 ? ?255 ? ?110 ? ?Rideal ? ?1000
*
***Buffer***
g260 ? ?260 ? ?110 ? ?255 ? ?110 ? ?0.001
R260 ? ?260 ? ?110 ? ?Rideal ? ?1000
*
***Buffer***
g265 ? ?265 ? ?110 ? ?260 ? ?110 ? ?0.001
R265 ? ?265 ? ?110 ? ?Rideal ? ?1000
*
***Buffer***
g270 ? ?270 ? ?110 ? ?265 ? ?110 ? ?0.001
R270 ? ?270 ? ?110 ? ?Rideal ? ?1000
*
***Buffer***
e280 ? ?280 ? ?110 ? ?270 ? ?110 ? ?1
R280 ? ?280 ? ?285 ? ?Rideal ? ?10
*
***Peak: f=3100MHz, Zeta=1.6, Gain=2.6dB***
e290 ? ?290 ? ?110 ? ?285 ? ?110 ? ?1
R290 ? ?290 ? ?292 ? ?Rideal ? ?10
L290 ? ?290 ? ?291 ? ?0.16e-9
C290 ? ?291 ? ?292 ? ?16.429e-12
R291 ? ?292 ? ?110 ? ?Rideal ? ?28.656
e295 ? ?295 ? ?110 ? ?292 ? ?110 ? ?1.349
*
*
***Output Stage***
g300 ? ?300 ? ?110 ? ?295 ? ?110 ? ?0.001
R300 ? ?300 ? ?110 ? ?Rideal ? ?1000
e301 ? ?301 ? ?110 ? ?300 ? ?110 ? ?1
Rout ? ?302 ? ?303 ? ?Rideal ? ? 19
Lout ? ?303 ? ?310 ? ? 3.6e-9
Cout ? ?310 ? ?110 ? ? 1.25e-12
*
*
***Output Current Limit***
H1 ? ?301 ? ?304 ? ?Vsense1 ? ?100
Vsense1 ? ?301 ? ?302 ? ?dc ? ?0
VIoutP ? ?305 ? ?304 ? ?dc ? ?11.836
VIoutN ? ?304 ? ?306 ? ?dc ? ?11.836
DIoutP ? ?307 ? ?305 ? ?diode
DIoutN ? ?306 ? ?307 ? ?diode
Rx3 ? ?307 ? ?300 ? ?Rideal ? ?0.001
*
*
***Output Clamp-2***
VoutP1 ? ?111 ? ?73 ? ?dc ? ?1.685
VoutN1 ? ?74 ? ?112 ? ?dc ? ?1.685
DVoutP1 ? ?75 ? ?73 ? ?diode
DVoutN1 ? ?74 ? ?75 ? ?diode
RX4 ? ?75 ? ?310 ? ?Rideal ? ?0.001
*
*
***Supply Currents***
FIoVcc ? ?314 ? ?110 ? ?Vmeas8 ? ?1
Vmeas8 ? ?310 ? ?311 ? ?dc ? ?0
R314 ? ?110 ? ?314 ? ?Rideal ? ?1e9
DzOVcc ? ?110 ? ?314 ? ?diode
DOVcc ? ?102 ? ?314 ? ?diode
RX5 ? ?311 ? ?312 ? ?Rideal ? ?0.001
FIoVee ? ?315 ? ?110 ? ?Vmeas9 ? ?1
Vmeas9 ? ?312 ? ?313 ? ?dc ? ?0
R315 ? ?315 ? ?110 ? ?Rideal ? ?1e9
DzOVee ? ?315 ? ?110 ? ?diode
DOVee ? ?315 ? ?103 ? ?diode
*
*
***Output Switch***
S4 ? ?104 ? ?313 ? ?113 ? ?106 ? ?Switch
*
*
*** Common Models ***
.model ? ?diode ? ?d(bv=100)
.model ? ?Switch ? ?vswitch(Von=2.205,Voff=2.195,ron=0.001,roff=1e6)
.model ? ?DzVoutP ? ?D(BV=4.3)
.model ? ?DzVoutN ? ?D(BV=4.3)
.model ? ?DzSlewP ? ?D(BV=257.194)
.model ? ?DzSlewN ? ?D(BV=257.194)
.model ? ?DVnoisy ? ?D(IS=5.51e-16 KF=1.09e-14)
.model ? ?DINnoisy ? ?D(IS=7.97e-17 KF=2.45e-15)
.model ? ?DIPnoisy ? ?D(IS=7.97e-17 KF=2.45e-15)
.model ? ?Rideal ? ?res(T_ABS=-273)
*
.ends
*
*
* Copyright (c) 1998-2021 Analog Devices, Inc. ?All rights reserved.
*
.subckt ADA4860 1 2 3 4 5 6
Cinp INp 0 {Cinp} Rpar={Rinp} Noiseless
Ibp INp 0 {Ibp}
Ibn N003 0 {Ibn}
Berr 0 Err I=(V(Binp,Binn)/{Rinn})*V(GO) Rpar=1
Ro N007 N003 {Rinn} Noiseless
G1 0 N004 Zol5 0 10
R1 N004 0 100m Noiseless
A1 6 4 0 0 0 _PD 0 0 SCHMITT Vt={PDVt} Vh=10m Trise={PDTon*2} Tfall={PDToff*2} Vlow=0 Vhigh=1
A2 0 N003 0 0 0 0 0 0 OTA G=0 In={Inn} Ink={Inkn}
A3 0 INp 0 0 0 0 0 0 OTA G=0 In={Inp} Ink={Inkp}
G3 0 Zol2 Vclamp 0 1m
C1 Zol2 0 {Cfp2} Rpar=1k Noiseless
G4 0 Zol3 Zol2 0 1m
C2 Zol3 0 {Cfp2} Rpar=1k Noiseless
Cinn N003 0 {Cinn}
Binp 0 Binp I=Uplim(Dnlim(V(INp)+{Vos}, V(Vcm_min), 0.3), V(Vcm_max), 0.3) Rpar=1
Binn 0 Binn I=Uplim(Dnlim(V(2), V(Vcm_min), 0.3), V(Vcm_max), 0.3) Rpar=1
R2 Zol1 0 {Zol} Noiseless
R3 N003 2 1? Noiseless
R4 INp 1 1? Noiseless
Bpd 6 0 I={Ipd_off}+V(_PD)* {Ipd_on-Ipd_off}
Bq 3 4 I={Iq_off}+V(_PD)* {Iq_on-Iq_off}+V(Imon)
G7 0 Vs 3 4 1m
R9 Vs 0 1k Noiseless
A7 VminGD 0 _PD 0 VmaxGD 0 GO 0 AND Tau=1n
A5 Vs 0 0 0 0 0 VminGD 0 SCHMITT Vt={Vsmin-50m} Vh=10m Tau=1n
A6 Vs 0 0 0 0 VmaxGD 0 0 SCHMITT Vt={Vsmax-50m} Vh=10m Tau=1n
R_Iout N004 N002 1?
Bimon 0 Imon I=1m*I(R_Iout) Rpar=1k Cpar=1p
Bhi 0 Hi I=1m*(V(3)-Table(V(Imon), 4m, 0.9, 20m, 1.9, 27m, 3, 85m, 5)) Rpar=1k
Blo 0 Lo I=1m*(V(4)+Table(-V(Imon), 4m, 0.9, 20m, 1.9, 27m, 3, 85m, 5)) Rpar=1k
A4 0 Err 0 0 0 0 Zol1 0 OTA G=1 Cout={Cfp1} Asym Isrc={Isrc} Isink={Isink} En={En} Enk={Enk} Vhigh=1e308 Vlow=-1e308
BVclamp 0 Vclamp I=1m*Uplim(Dnlim(V(ZOL1), V(Lo), 0.3), V(Hi), 0.3) Rpar=1k
D2 N002 5 Iscp
D1 5 N002 Iscn
G11 0 Zol4 Zol3 0 1m
C8 Zol4 0 {Cfp2} Rpar=1k Noiseless
G12 0 Zol5 Zol4 0 1m
C9 Zol5 0 {Cfp2} Rpar=1k Noiseless
Bbuf 0 N007 I=(V(INp) +{Vos})*V(GO)
R11 N007 0 1
BVcm_min 0 Vcm_min I=V(4)+{Vcm_min} Rpar=1
BVcm_max 0 Vcm_max I=V(3)+{Vcm_max} Rpar=1
.param Rinp=12Meg Cinp=1.5p
.param Rinn=90 Cinn=680f
.param Zol=700k fp1=260k fp2=3.2G fp3=1T
.param SRp=980 SRn=-790
.param En=4n Enk=450
.param Inp=1.5p Inkp=7k
.param Inn=7.7p Inkn=1.75k
.param Vcm_min=1.2 Vcm_max=-1.3
.param Vos=-3.5m
.param Ibp=-1u Ibn=1.5u
.param PDVt=0.6 PDTon=200n PDToff=3.5u
.param Ipd_on=130u Ipd_off=-250n
.param Iq_on=6m Iq_off=250u
.param Vsmin=5 Vsmax=12
.param Iscp=85m Iscn=-85m
.param Cfp1 = {1 / (2 * pi * fp1 * Zol)}
.param Cfp2 = {1 / (2 * pi * fp2 * 1k)}
.param Cfp3 = {1 / (2 * pi * fp3 * 1k)}
.param Isrc = {Cfp1 * SRp * 1e6}
.param Isink= {Cfp1 * SRn * 1e6}
.model Iscp D(Ron=1m Roff=1G Ilimit={Iscp} Epsilon=50m)
.model Iscn D(Ron=1m Roff=1G Ilimit={-Iscn} Epsilon=50m)
.ends ADA4860
*
*
.subckt ADA4530-1 1 2 3 4 5 6
B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-.2, .1)+1n*V(1)
B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-.21, .1)+1n*V(2)
C10 N004 0 1f Rpar=100K noiseless
D9 N008 0 DLIM
C13 3 4 10p
A1 0 2 0 0 0 0 0 0 OTA g=0 in=.07f
G1 0 N016 5 Mid 100m
C8 N008 N016 38p
C6 2 4 4p Rser=100k noiseless
A4 N004 0 0 0 0 0 N007 0 OTA g=1m linear enk=330 en=13.8n*(1+freq/5Meg) Rout=1k Cout=15p Vlow=-1e308 Vhigh=1e308
C7 3 2 4p Rser=100k noiseless
A7 0 N006 0 0 0 0 N008 0 OTA g=500u linear Cout=10f Vhigh=1e308 Vlow=-1e308
D3 3 4 DBURN
G5 0 Mid 3 0 .5m
G6 0 Mid 4 0 .5m
R4 Mid 0 1K noiseless
M1 5 N014 4 4 NI temp=27 M=10
C2 3 5 1p Rpar=1G Rser=10k noiseless
M2 5 N009 3 3 PI temp=27 M=10
A2 3 N009 4 4 4 4 N014 4 OTA g=1u linear ref=1.4 vlow=0 vhigh=3.4
C3 3 N009 1f Rpar=1Meg Rser=500k noiseless
A3 0 N010 3 3 3 3 N009 3 OTA g=20u linear ref=-37.7515m vlow=-3.5 vhigh=2.5
C11 N014 4 1p Rpar=1Meg Rser=10Meg noiseless
D4 5 4 DoutMin
D5 3 5 DoutMin
S1 N008 0 4 3 SNLG
C4 3 1 4p Rser=100k noiseless
C5 1 4 4p Rser=100k noiseless
C12 N008 0 2p
C19 N009 5 1.5p Rser=75k noiseless
M3 3 N011 6 6 NG temp=27
M4 4 N011 6 6 PG temp=27
C17 3 6 500f
C21 6 4 500f
C22 N011 Mid 28.937f Rpar=2Meg noiseless
G3 Mid N011 1 Mid 1?
S2 N011 Mid N011 3 Suplim
A5 1 0 0 0 0 0 0 0 OTA g=0 in=.07f
D6 2 6 DIN
D7 6 1 DIN
C23 2 6 200f
C25 6 1 200f
C14 N016 0 3n Rser=20 Rpar=10 noiseless
C9 5 4 1p Rpar=1G Rser=10k noiseless
A6 0 N005 0 0 0 0 N006 0 OTA g=1m linear Rout=1k Cout=15p vlow=-105.5m vhigh=105.5m
C15 N005 0 15p Rpar=1k noiseless
A9 0 N008 0 0 0 0 N010 0 OTA g=20m iout=1m Rout=1k Cout=40p vlow=-1e308 vhigh=1e308
G2 0 N005 N007 0 1m
C1 5 N014 1.5p Rser=1Meg noiseless
.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=500m ilimit=703.57u noiseless)
.model DoutMin D(Ron=100 Roff=100 ilimit=20u noiseless)
.model SNLG SW(level=2 Ron=2Meg Roff=50Meg vt=-3 vh=-1.5 noiseless)
.param CL=10p
.model PI VDMOS(kp=280u vto=-500m mtriode=2.3 ?ksubthres=100m pchan noiseless)
.model NI VDMOS(kp=700u vto=500m mtriode=1.6 ?ksubthres=100m noiseless)
.model DLIM D(Ron=1k Roff=2G Vfwd=1.8 Vrev=1.8 epsilon=100m revepsilon=100m noiseless)
.model PG VDMOS(kp=1.72m vto=300m mtriode=2 ksubthres=100m pchan noiseless)
.model NG VDMOS(kp=1.72m vto=-300m ksubthres=100m noiseless)
.model Suplim SW(Ron=1 Roff=2Meg vt=-1.39 vh=-100m noiseless)
.model DIN D(Ron=1k Roff=30T vfwd=600m epsilon=300m vrev=600m revepsilon=300m noiseless)
.ends ADA4530-1
*
*
*
.subckt ADA4530 1 2 3 4 5 6
B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)-1.4,.1), V(4)-.2, .1)+1n*V(1)
B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)-1.39,.1), V(4)-.21, .1)+1n*V(2)
C10 N004 0 1f Rpar=100K noiseless
D9 N008 0 DLIM
C13 3 4 10p
A1 0 2 0 0 0 0 0 0 OTA g=0 in=.07f
G1 0 N016 5 Mid 100m
C8 N008 N016 38p
C6 2 4 4p Rser=100k noiseless
A4 N004 0 0 0 0 0 N007 0 OTA g=1m linear enk=330 en=13.8n*(1+freq/5Meg) Rout=1k Cout=15p Vlow=-1e308 Vhigh=1e308
C7 3 2 4p Rser=100k noiseless
A7 0 N006 0 0 0 0 N008 0 OTA g=500u linear Cout=10f Vhigh=1e308 Vlow=-1e308
D3 3 4 DBURN
G5 0 Mid 3 0 .5m
G6 0 Mid 4 0 .5m
R4 Mid 0 1K noiseless
M1 5 N014 4 4 NI temp=27 M=10
C2 3 5 1p Rpar=1G Rser=10k noiseless
M2 5 N009 3 3 PI temp=27 M=10
A2 3 N009 4 4 4 4 N014 4 OTA g=1u linear ref=1.4 vlow=0 vhigh=3.4
C3 3 N009 1f Rpar=1Meg Rser=500k noiseless
A3 0 N010 3 3 3 3 N009 3 OTA g=20u linear ref=-37.7515m vlow=-3.5 vhigh=2.5
C11 N014 4 1p Rpar=1Meg Rser=10Meg noiseless
D4 5 4 DoutMin
D5 3 5 DoutMin
S1 N008 0 4 3 SNLG
C4 3 1 4p Rser=100k noiseless
C5 1 4 4p Rser=100k noiseless
C12 N008 0 2p
C19 N009 5 1.5p Rser=75k noiseless
M3 3 N011 6 6 NG temp=27
M4 4 N011 6 6 PG temp=27
C17 3 6 500f
C21 6 4 500f
C22 N011 Mid 28.937f Rpar=2Meg noiseless
G3 Mid N011 1 Mid 1?
S2 N011 Mid N011 3 Suplim
A5 1 0 0 0 0 0 0 0 OTA g=0 in=.07f
D6 2 6 DIN
D7 6 1 DIN
C23 2 6 200f
C25 6 1 200f
C14 N016 0 3n Rser=20 Rpar=10 noiseless
C9 5 4 1p Rpar=1G Rser=10k noiseless
A6 0 N005 0 0 0 0 N006 0 OTA g=1m linear Rout=1k Cout=15p vlow=-105.5m vhigh=105.5m
C15 N005 0 15p Rpar=1k noiseless
A9 0 N008 0 0 0 0 N010 0 OTA g=20m iout=1m Rout=1k Cout=40p vlow=-1e308 vhigh=1e308
G2 0 N005 N007 0 1m
C1 5 N014 1.5p Rser=1Meg noiseless
.model DBURN D(Ron=100 Roff=1G vfwd=600m epsilon=500m ilimit=703.57u noiseless)
.model DoutMin D(Ron=100 Roff=100 ilimit=20u noiseless)
.model SNLG SW(level=2 Ron=2Meg Roff=50Meg vt=-3 vh=-1.5 noiseless)
.param CL=10p
.model PI VDMOS(kp=280u vto=-500m mtriode=2.3 ?ksubthres=100m pchan noiseless)
.model NI VDMOS(kp=700u vto=500m mtriode=1.6 ?ksubthres=100m noiseless)
.model DLIM D(Ron=1k Roff=2G Vfwd=1.8 Vrev=1.8 epsilon=100m revepsilon=100m noiseless)
.model PG VDMOS(kp=1.72m vto=300m mtriode=2 ksubthres=100m pchan noiseless)
.model NG VDMOS(kp=1.72m vto=-300m ksubthres=100m noiseless)
.model Suplim SW(Ron=1 Roff=2Meg vt=-1.39 vh=-100m noiseless)
.model DIN D(Ron=1k Roff=30T vfwd=600m epsilon=300m vrev=600m revepsilon=300m noiseless)
.ends ADA4530
*
<###
"
Re: LTspice Help

 

Problem fixed ... found out how to make Microsoft Edge open .html files, instead of Notepad, in my Laptop App Settings ... bingo ... I must have set up Notepad as the Default when I was adding 3rd party models to my Spice Libraries.? Another Brick in the Wall.
Ian ... :)
Re: LTspice Help

 

Hi Andy and esims,
?
Re: this Group web site .... I searched the Files, Database and Wiki sections but did not think to look in the Home page .... :(
Re: Analog Devices .... I have searched that site several times and only found this page ?? which is 24.1.6? or LTspice XVII ... :(
That said, I can download 24.0.12 from both sources.
?
I tried the "Repair" option provided in the LTspice download ... no change;? I did an Uninstall and Re-install with the same outcome.??
?
LTspice Help Menu did function on this laptop until recently ..... so my problem must be some File/Program Property(??) that I have selected wittingly or unwittingly ... veeeerrryyyy frustrating that I don't understand this stuff sufficiently to fix it myself ... I will delve into File associations and?html .... gulp.
?
Thanks,
Ian
Re: "Flaw" in UniversalOpamps

 

I also remember looking at this, several years ago.
?
This should be fixed. For practical components, the common mode I/P impedance is always higher than the differential I/P impedance. So, I'd say this was a bug.
Is it possible that this behavior was intentional?? It seems unlikely, but ....
?
Might it have been done this way to be compatible with op-amp behavioral models in certain other SPICE simulators?? Does PSpice (for example) have a "universal" op-amp behavioral model too?
?
Would fixing this now "break" existing simulations?
?
Would you trust handing it over to someone to fix it, and having them not also "fix" other things that did not need fixing?? I do not have much confidence in that right now.? They break things that did not need to be broken - even if they later unfix the things they broke.? They do not seem to have the wisdom and maturity to leave some things alone.
?
Andy
?
Re: LTspice Help

 

Ian,

Analog Devices also still hosts old versions directly on their site.

Eric


On Tue, Apr 8, 2025, 8:26?PM Andy I via <AI.egrps+io=[email protected]> wrote:
On Tue, Apr 8, 2025 at 08:01 PM, tinkera123 wrote:
I have been searching for a source to re-download 24.012.
Have you looked at our group's main webpage?? It has links to a few of the older versions on it, including version 24.0.12.
?
I did find a couple of sites offering 24.012 downloads but I have no idea of their trustworthiness.? Is there a reputable source of older Versions for downloads?
See above.? I would rate that very trustworthy.
?
Andy
?
Re: LTspice Help

 

On Tue, Apr 8, 2025 at 08:01 PM, tinkera123 wrote:
I have been searching for a source to re-download 24.012.
Have you looked at our group's main webpage?? It has links to a few of the older versions on it, including version 24.0.12.
?
I did find a couple of sites offering 24.012 downloads but I have no idea of their trustworthiness.? Is there a reputable source of older Versions for downloads?
See above.? I would rate that very trustworthy.
?
Andy
?
Locked Re: Design a DC DC converter using NE555

 

I have locked this topic.
Locked Re: Design a DC DC converter using NE555

 

On Tue, Apr 8, 2025 at 10:08 PM, <otherappuser@...> wrote:

A dc-dc converter which has to supply an output voltage of 5 V with the output power from 2.5 W to 25 W. ...

Is that a homework assignment?

Please note that this group does not condone solving homework assignments for students who are too lazy to do the work yourself.? If this was an assignment for you to solve, then for heaven's sake do it yourself and don't ask anyone else to do it.? That is called cheating.? Are you a cheat??
?
If not, prove to us why you are not.
?
Regardless, are you really that lazy that you can't even begin to start this problem yourself?
?
Anyway, this is a group about LTspice.
?
Andy
?
Locked Re: Design a DC DC converter using NE555

 

My apologies for the duplicate identical messages from "otherappuser".? Partly my fault.? I've deleted the second one.
?
Andy
?
Locked Design a DC DC converter using NE555

[email protected]
 

A dc-dc converter which has to supply an output voltage of 5 V with the output power from 2.5 W to 25 W. The variation of the output voltage of ¡À5% is acceptable, however, the high frequency ripple resulting from the switching process has to be limited to ¡À1% in order to control the noise problems. The converter is to operate from various dc sources within a range of 9 V to 16 V. You can assume that apart from the amplitude variation the input source is an ideal voltage source. The isolation is not required for this converter. The design includes a control system. The output voltage should be used for full feedback control. The only energy source in the system is the input source, therefore the power for the supply of the control block needs also to be drawn from the input source. As the power dissipation of the control block is very small compared with the load power, you can use a simple voltage regulator for this power supply. We can use the following components to design in LT spice using NE555

?

? ?Resistors, including variable resistors,? ??Capacitors,?Inductors,? ?Diodes,? ??Zener diodes,? ??Bipolar transistors,? ??NE555 precision timer
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