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Re: Convergence problem with Sallen-Key filter circuit
¿ªÔÆÌåÓýIt's not about convergence really; LTspice cannot find the DC operating point easily.? If you add the Spice directive .option gminsteps=0, the simulation runs and gives credible results for the AC sweep. By the way, asking for 10 thousand points per
decade in your AC sweep is huge overkill, especially as you are
sweeping over many decades. Best wishes John Woodgate OOO-Own Opinions Only J M Woodgate and Associates Rayleigh, Essex UK On 2018-12-02 16:34,
einballinderwueste@... [LTspice] wrote:
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Re: Convergence problem with Sallen-Key filter circuit
¿ªÔÆÌåÓýJan wrote:"I'm trying to simulate a Sallen Key filter with a cutoff frequency of around 40kHz using a unipolar 5V source (See TEMP section). The initial operating point solution does not converge. I have added series resistances everywhere so every point in the circuit has a connection to GND as described in Since I cannot find any problem in my circuit, I'm out of ideas on where LTSpice might fail. Can someone hint me to where the problem might be?" Your circuit converges fine and runs with .options gminsteps=0. It make no sense to have 10000 points per decade in an .AC analysis, unless you have a circuit with a Q of 1000s - I changed it to 24. It just takes longer and you produce a huge .RAW file. Regards, Tony |
Re: Convergence problem with Sallen-Key filter circuit
Jan wrote, "The initial operating point solution does not converge.?" Actually, it does.? But the Gmin Stepping algorithm has trouble, and either runs a very long time or never finishes.? We see this from time to time.? I don't know why LTspice seems to get stuck on one algorithm instead of moving on, but it happens occasionally. LTspice has a handful of different algorithms that it tries when looking for the DC operating point.? It's supposed to know when one isn't working, and move on to try the next, and so on.? In your circuit's case, the Direct Newton-Raphson Iteration algorithm quickly fails, and then the Gmin Stepping algorithm tries but seems to keep trying forever.? So you need to tell LTspice to skip that algorithm: ? ? .options GminSteps=0 I see that you had that on your schematic, but it is commented out (ineffective). Alternatively, you can press the Esc key when it's trying (forever) in that algorithm, and it moves on to the next one.? Watch the status messages in the lower left corner.? "Press Esc to quit" doesn't quit LTspice; it only quits the current algorithm.? Your circuit converges OK with either the Source Stepping or the Pseudo Transient algorithms. See this Help page: LTspice > Dot Commands > .OP -- Find the DC Operating Point Regards, Andy
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Re: Drag/Drop circuit from one window into another
¿ªÔÆÌåÓý
1. Select Duplicate (F6) 2. Frame the area to be selected. 3. Click on the target window 4. drag the circuit which then hangs at the cursor 5. drop it into the target window. Thanks, got it. (Forgot to select the raget window while the copy action was still active)
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Convergence problem with Sallen-Key filter circuit
Hello there group members, I'm trying to simulate a Sallen Key filter with a cutoff frequency of around 40kHz using a unipolar 5V source (See TEMP section). The initial operating point solution does not converge.? I have added series resistances everywhere so?every point in the circuit has a connection to GND as described in? Since I cannot find any problem in my circuit, I'm out of ideas on where LTSpice might fail.? Can someone hint me to where the problem might be? ? Best regards, Jan |
Re: Drag/Drop circuit from one window into another
¿ªÔÆÌåÓýIn order to copy a schematic or part of one to
another schematic, you have to have both schematics open in the
same instance of LTspice. Open them both before you try to copy. Best wishes John Woodgate OOO-Own Opinions Only J M Woodgate and Associates Rayleigh, Essex UK On 2018-12-02 14:34, kuku@...
[LTspice] wrote:
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Drag/Drop circuit from one window into another
I thought it would work to select/duplicate a portion of a schematic and drag it into a new window? But for the moment I can't find the protocol how to perform this. With a copied circuit hanging on the cursor it's possible to open a new sheet on the fly and drop the circuit into that. But how can I insert the circuit into an existing one which is currently open in the multiple window view? -- Christoph |
Re: Hilighting a voltage in schematics
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Thanks, nice trick.? ¡ª Christoph |
Re: Hilighting a voltage in schematics
I name all nodes that might be "interesting" so I know where everything is.
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Donald. -- *Plain Text* email -- it's an accessibility issue () no proprietary attachments; no html mail /\ <> On 2018-12-02 6:02 a.m., kuku@... [LTspice] wrote:
To find a signal name in the schematics, is it possible to highlight this signale, e.g. from the plot view? |
Re: Auto loadbias and savebias for stepped simulations
Hello analogspiceman
I recently asked Mike if would be possible to add a new feature to .savebiasWhat was his response? I'm also curious because, by chance, I saw this topic come up on electronics.stackexchange a few days ago. -- Vlad ______________________ ltspicegoodies.ltwiki.org -- holding, among others: a universal analog/digital filter, block-level models for power electronics (and not only), math blocks with a more stream-lined approach, some digital ADC, DAC, (synchronous-)counter, JKflop, etc. |
Auto loadbias and savebias for stepped simulations
I recently asked Mike if would be possible to add a new feature to .savebias and .loadbias invoked by the keyword ¡°eachstep¡± whereby in a stepped simulation, each succeeding step would load the bias saved by the preceding step.? Among other uses, this could allow eliminating the startup transient between steps when performing a time domain frequency response analysis. Currently bias data may be saved from individual steps, but the syntax is cumbersome as each step must be specified: .savebias bias1.txt time=1m step=0 Unfortunately, there is no way to load different bias data for steps, which is the reason for my request to Mike.
.subckt L 1 2 .param L=1 Rser=1m Rpar=1/Gmin C1 3 0 {L} Rser={1/Rpar} Rpar={1/Rser} G1 1 2 3 0 1 G2 3 0 2 1 1 .ends L ? Merry Christmas and a Happy New Year |
Re: What does Heightened Def Con mean ?
wgrandner wrote, "What does Heightened Def Con mean ?" It means LTspice is having some trouble, but hasn't given up yet. In your case, it may mean there is something in your circuits that is making LTspice unhappy. Here is a very old message, from the master himself (LTspice's author): ? ?? ? ? Def Con" comes from the term DEFCON or DEFense CONdition. ? ? In public service, this runs from 5 to 1. The lowest state ? ? of defensive readiness is condition 5, meaning normal ? ? peacetime. DEFCON 1 is the highest defensive condition ? ? readiness and means the country is at war. ? ? In LTspice, the scale is reversed, Def Con 0 means it's ? ? having no trouble solving the circuit and increases with ? ? circuit difficulty. Its main use for macro models circuits ? ? is to let you gauge a bit as to how robust the model is. ? ? I haven't looked at your circuit, bit it sounds like you ? ? might be exciting some some kind of a race condition in the ? ? model. Don't forget to try the alternate solver when you ? ? have convergence problems. ? ? --Mike Note the mention of the Alternate Solver.? It might (or might not) help eliminate those messages.? The Alternate Solver is usually more accurate, but slower; but in some cases it can be the other way around.? Don't forget that the Alternate Solver is a "sitcky" setting, so it remains selected until you un-select it. Regards, Andy |
Re: Is it possible to dynamically change a part's location in one simulation ?
ericsson.sunshine, There are lots of problems with your?20181130_subckt_stepping_ng_FFSD08120A_2p.zip example. You should start simple, then build up to more complex, not the other way around.? When you dive right in with many untried things, it's a good way to fail.? Get the simple case working first, before moving to more complex.? It's better to debug one thing at a time, instead of many at once. MODELs and SUBCKTs are never interchangeable.? It's one or the other. OnSemi's models are SUBCKTs, not MODELs.? Also, your diode symbol has Prefix = X, so it can ONLY use a SUBCKT.? Therefore, don't try the .MODEL statements. I do not believe that "AKO" can be used with SUBCKTs.? I think I have only seen it used with MODELs, not SUBCKTs, and I don't know how they could be used with subcircuits.? Also, every .SUBCKT line must be paired with an .ENDS line. There is no FFSD08120A_2p in OnSemi's library file. As I said earlier, STEPping SUBCKTs is potentially very dangerous.? It's not like STEPping MODELs.? Do you know that both subcircuits are fundamentally the same, inside?? Do you even know what's inside them?? Unless you are certain that both subcircuits have the same internal structure, I would advise against STEPping them. However, if you insist on taking that risk, here's one way to do it.? Encapsulate the subcircuits inside your own subcircuits named 1 and 2.? I will upload an example of this to the Temp folder. Here are more examples in the group's Files area for STEPping SUBCKTs: ? ? Files > Tut > Stepping to the max > stepping_subckt.asc ? ? Files > Tut > Stepping to the max > stepping_opamp_models1.asc ? ? Files > Tut > Stepping to the max > stepping_opamp_models1.asc ? ??Regards, Andy |
Re: The simulation of the LTspice is blocked with sentence (if)
j.bernabe1 wrote: ? ? "I want to simulate a power supply with the statement (if) using the generator (bv.asy), and with the following condition : ? ? ?V=if(V(Vsense)>1.2,1,0)?? ? ? ?... ? ? ?The simulation do not work, is blocked,?It does not perform the transient analysis." I tried it, and it worked.? So, I guess you made a mistake.? Helmut's reply was correct, but I think you already did that. You also tried this: ? ? "V ={si(V(Vsense)>1.2,1,0)}" but that does not work because "si" is not a valid function name in LTspice.? It must be "if". ? ? "I would like to know the reason of the not simulation. ? ? ?You? know?the reasons why the simulation? does not work ?" None of us can say, because (1) we don't know what the error message was, and (2) we can't see your schematic.? The error message probably was not "blocked"; it probably was something else, and it said what was wrong. Please consider uploading your schematic to the "Temp" folder.? Also, please be more helpful by telling us the actual error message. Regards, Andy |
The simulation of the LTspice is blocked with sentence (if)
Hi, friends.
I have a question, have a problem with the simulation about the sentence (if). I want to simulate a power supply with the statement (if) using the generator (bv.asy), and with the following condition : V=if(V(Vsense)>1.2,1,0)?? I have also tried with this : V ={si(V(Vsense)>1.2,1,0)} The simulation do not work, is blocked,?It does not perform the transient analysis.? I would like to know the reason of the not simulation. You? know?the reasons why the simulation? does not work ? AHh,?that generator is connected to the non-inverting input of the LTC6752 comparator. I wait can to have a good help, because for me, this simulation is very important, is for a innovative electronic design . Sorry by my bad level english. |