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I have found and used the BSR202N model and test circuit from Tony(?) The test circuit worked - but in my circuit - I ma getting similar results to that from my original version of the infineon model.

Hello, Andy: The mentioned ideas was not from me, and not related to what I said about 'confidential'. Just a brief, sudden thoughts, but I certainly remembered that someone who had written some thing

Hello, LTspice has a phase comparator named "phidet". It*s in the folder [Digital]. The deafult output curernt is 100uA. This current can be set to any other value with Iout=xxx. See the example

Would anyone be able to direct me towards some accurate phase comparator circuits that I could build within LTspice XVII? Thanks

I still don't know what the Bv is for. Since it represents an unreal component, are you thinking about using it to experiment with an altered circuit, before designing that "alteration" using real

Marcel wrote: "Still, they are all schematics created by this particular user. Maybe he has a special lib, or uses specific LTspice features. It would help to see the smallest complete project that

Hello Helmut, I agree in principle for transient simulations, but for DC sweeps it does make sense because the case to junction temperature difference would otherwise be zero, as you say. Regards,

Hello Tony, You shouldn't normally connect a V-source to the output TJ, because this pin is internally driven and shows the junction temperature. The output will be very different when you remove V4,

richard@... wrote: "Are there any "tricks of the trade" translating Pspice models for use in LTspice? Not sure how to upload or share the models or ASC files. Happy to do so with

To upload, go to the web site, click on Files, scroll to Temp and click on Upload. Upload a ZIP archive (not any other sort) containing everything required to run the simulation, but not .raw or .log

I am trying to use the Infineon supplied Pspice model for this part (BSR202N). I've created (found) a 5 terminal symbol to suit the model, but it makes no sense in an LTspice simulation. If I replace

For example, (not adapted by me), the typically active PF controller makes the PF upto very high 99%, but after EMI filter circuit added, maybe some phase difference may be caused, those phase

Still, they are all schematics created by this particular user. Maybe he has a special lib, or uses specific LTspice features. It would help to see the smallest complete project that crashes. -marcel

Hello, Andy: Let me ask this: What are you trying to do? Why add the Bv sources? Just some quick transfer trying for compensation to a newer shape as the secondary reference, concurrently with the

Hello. I offered to Google translator another translation option: operating point ==> operatsionnaya tochka (in Russian in Latin letters) Thanks to Andy for the clarification. Bordodynov. 14.11.2018,

An interesting thing......is ... Those phenomemon in other software eg: PSIM, the math parsing won't take any effect with those loading effect. This might confused me to do those kind of

Ericsson.sunshine, Without running any simulation yet, it looks like your second uploaded example (LT1249) could be a problem too. The Vsense and VAout pins are the input and output pins of the error

Hi, Andy: Sorry, I saw the blindpoint. The BV didn't the connection of two nodes, it's a new voltage source. So the errOP's peripheral won't work as expect, after I added a 10K resistor between the BV

Hi, Andy: Thank you for the replies, I'm sorry, it's too rush, so made this mistake. I have uploaded another example which uses the LT1249, typically the FB is resistor divided, the current sinked

Ericsson.sunshine, Regarding your circuit in 20181115_BV,BI behavioral device FB pin test failure desc.zip: I think you forgot about the current through R2 and the voltage drop across it. The original