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Re: .MEAS Failure

 

Hello All:
?
.meas TooLow1 FIND V(XSW11:X1:Qc,XSW11:X1:Qe) WHEN V(XSW11:X1:Qc,XSW11:X1:Qe)=2 FALL=1
works and produces;
toolow1: v(xsw11:x1:qc,xsw11:x1:qe)=2 at 0.00804696
?
Zooming in the plot window to the end of the universe, I see this point.
8.0469636ms 2.0000203V
The next point is:
8.0469636ms 1.9999355V
The time values must have greater precision than can be seen because a node can't have two different voltages at the same time.
I now see that since there is no value in the data that is exactly 2.0000000 it had to perform a poor mans less-than function.
The code saw that 1.9999355 was less-than 2 where the previous sample 2.0000203 was more than two.
So that's a fall.
There was no test to see if data was ever == 2 as the .MEAS statement would imply.
I now see that the Fall and Rise modifiers mimic less-than or greater-than behavior for the .MEAS FIND WHEN statement.
?
All for now
?
Sent:?Monday, February 24, 2025 at 12:17 PM
From:?"eewiz via groups.io" <eewiz@...>
To:[email protected]
Subject:?Re: [LTspice] .MEAS Failure
?
Hello All:
?
Sorry for being late to the party but I had to grab some sleep time.
?
So, it's equality only.
No matter how many times I read the .meas help I would not come to that conclusion.
To me;?WHEN <expr> means WHEN <any and all types of mathematical experssion>.
WHEN <expr of equality only> would be much more redily understandable.
?
I noticed that there were no examples of anything like:
Print the time if and when a power exceeds 5W.
Print the time if and when a collector-emitter voltage goes less than 2V.
Print the time if and when a snubbed node ever exceeds 15.6V.
?
Those are always the type of questions that I regularly need answers to.
?
Thanks very much for the examples.
I will see if I can get the answers I need using only equality.
?
All for now

?
Sent:?Monday, February 24, 2025 at 11:24 AM
From:?"Tony Casey via groups.io" <tony@...>
To:[email protected]
Subject:?Re: [LTspice] .MEAS Failure
On 24/02/2025 15:57, Andy I via groups.io wrote:
But I distinctly recall Helmut Sennewald cautioning people not to test for equality.? Better to use >= or <=.? The implication was that it did not use linear interpolation in those situations.? I thought .MEAS was one of them.
This would be the case, for example, in a B-source expression, which disallows the "=" operator anyhow, e.g.:
?
B1 EQ0 0 V=if(V(test)=0,1,0)

..which triggers an error, but:
?
B1 EQ0 0 V=if(V(test)==0,1,0)

..doesn't.

However, in the example of my simple sine source circuit, the 2nd of those expressions only results in V(eq0)=1 once at time=0, because none of the following data points result in V(test)=0, even though it is clear the waveform is periodic and passes through zero twice every cycle. This example therefore doesn't use interpolation, it simply looks at each data point.

--
Regards,
Tony


Re: intuition behind a solution to crashing time domain simulation #Time-step-too-small

 

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10f is recognized as 10 femtofarads.

On 2025-02-24 21:29, Bell, Dave via groups.io wrote:

Is “10f” a special case in the parasitics settings?

For a regular cap, it would mean 10 Farads!

?

From: [email protected] <[email protected]> On Behalf Of john23 via groups.io
Sent: Monday, February 24, 2025 12:29 PM
To: [email protected]
Subject: EXTERNAL: Re: [LTspice] intuition behind a solution to crashing time domain simulation #Time-step-too-small

?

?

?

The following line solved the problem.Is there some manual or intution regarding why these might help?

.options cshunt =10f gshunt=10n abstol=10n vntol=1m

?

Thanks.

--
OOO - Own Opinions only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion

Virus-free.


Re: intuition behind a solution to crashing time domain simulation #Time-step-too-small

 

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Is “10f” a special case in the parasitics settings?

For a regular cap, it would mean 10 Farads!

?

From: [email protected] <[email protected]> On Behalf Of john23 via groups.io
Sent: Monday, February 24, 2025 12:29 PM
To: [email protected]
Subject: EXTERNAL: Re: [LTspice] intuition behind a solution to crashing time domain simulation #Time-step-too-small

?

?

?

The following line solved the problem.Is there some manual or intution regarding why these might help?

.options cshunt =10f gshunt=10n abstol=10n vntol=1m

?

Thanks.


Re: intuition behind a solution to crashing time domain simulation #Time-step-too-small

 

?
?
The following line solved the problem.Is there some manual or intution regarding why these might help?
.options cshunt =10f gshunt=10n abstol=10n vntol=1m
?
Thanks.


Re: Monitor simulation percent completion from python

 

There is no way of knowing how large the .raw file will be.? Indeed, it might not be the same even for similar simulations.? It depends on how many time points LTspice actually used, which is not known until it's done.
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I suspect LTspice currently outputs no progress information when running in batch mode, and the only way to get that, would be by adding it (new feature) to LTspice.? As you know, this forum is not the place to request that.
?
Even having progress info., it can't tell you how much time is still needed.? A simulation might whiz through the first 90% and then take hours or days trudging through the last 5%.
?
Andy


Re: Initial conditions for inductor current in .TRAN UIC analysis - follow up

 

Apologize, I just wanted to make sure I understood it correctly :-)


Re: intuition behind a solution to crashing time domain simulation #Time-step-too-small

 

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I don't know what's going on here. U1 isn't open-loop. Are we looking at the same .ASC, PID_section_united_AC_separate?? U3 is open-loop at DC. U1 and U2 have unity gain, U4 has 100 times gain at DC. In such a circuit, I would not expect a TSTS? error, and I would expect the model o a costly opamp to be a good one. I meant that I could not see how to verify node 38 without going back over the previous many emails.

On 2025-02-24 17:19, Andy I via groups.io wrote:
On Mon, Feb 24, 2025 at 11:11 AM, John Woodgate wrote:

I agree, of course, but the AD797 is a (costly) opamp. It should not produce a TSTS error in that .ASC.

Why not?

Does expensive silicon imply an equally expensive SPICE model?? Shouldn't every SPICE model ever made, whether for cheap or expensive silicon, not produce time step too small errors?? And yet they happen.

Without a lot of digging, it isn't possible to confirm that it is connected correctly; for example, is node 38 really the output?

The SPICE model claims that it is.? What is your point with that question?? Are you suggesting that its creator at AAG/PMI did not know what she/he was doing, and mis-labeled the output node?? If that happened, then there would be an awful lot more questions than that one.
?
I think simpler circuits are in order for this simulation.? Realizing that U1 is open-loop might be a good first step.? Since this is a DC simulation, capacitors are open-circuits.? No negative feedback around U1.? U3 seems to run into difficulty right in the vicinity of 0 V output, which is odd.
?
Even when the circuit is made smaller and it runs, it has considerable difficulty at certain operating points.? The SPICE output log is foll of warning messages that suggest it has trouble, and it suggests alternative settings to help.
?
Andy
?
--
OOO - Own Opinions only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion


Re: Monitor simulation percent completion from python

 

Thanks Tony, I have a callback function for when the simulation finishes so the user gets notified via email. They are asking for percent completion because they are running simulations that take 3 days... and highlighting to me that you can see % completion in the GUI. I was wondering if I could parse one of the output files but probably the only way is just to show the current size of the raw file. You of course wouldn't have an idea of percent completion unless you knew approximately how large the raw file was expected to be though.


Re: Initial conditions for inductor current in .TRAN UIC analysis - follow up

 

On Mon, Feb 24, 2025 at 12:15 PM, Carlo wrote:
Do you mean it might try to compute another/different ITS pass ...
You appear to be extremely insistent by asking this question over and over, as if asking it every few minutes will twist my arm and force me to answer you immediately.
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I don't work that way.
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Go somewhere else.? Take your nagging to another forum.? Keep it up, and you'll be permanently out of here.
?
Andy
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Re: .MEAS Failure

 

On Mon, Feb 24, 2025 at 11:24 AM, Tony Casey wrote:
On 24/02/2025 15:57, Andy I via groups.io wrote:
But I distinctly recall Helmut Sennewald cautioning people not to test for equality.? Better to use >= or <=.? The implication was that it did not use linear interpolation in those situations.? I thought .MEAS was one of them.
This would be the case, for example, in a B-source expression, which disallows the "=" operator anyhow, e.g.:

B1 EQ0 0 V=if(V(test)=0,1,0)

..which triggers an error, but:

B1 EQ0 0 V=if(V(test)==0,1,0)

..doesn't.
Yeah - that is a different problem, caused by misusing operators.
?
Helmut's concern was over the lack of exact equality.? I guess it applied only in specific situations, which did not include this one.
?
Andy
?


Re: intuition behind a solution to crashing time domain simulation #Time-step-too-small

 

On Mon, Feb 24, 2025 at 11:11 AM, John Woodgate wrote:

I agree, of course, but the AD797 is a (costly) opamp. It should not produce a TSTS error in that .ASC.

Why not?

Does expensive silicon imply an equally expensive SPICE model?? Shouldn't every SPICE model ever made, whether for cheap or expensive silicon, not produce time step too small errors?? And yet they happen.

Without a lot of digging, it isn't possible to confirm that it is connected correctly; for example, is node 38 really the output?

The SPICE model claims that it is.? What is your point with that question?? Are you suggesting that its creator at AAG/PMI did not know what she/he was doing, and mis-labeled the output node?? If that happened, then there would be an awful lot more questions than that one.
?
I think simpler circuits are in order for this simulation.? Realizing that U1 is open-loop might be a good first step.? Since this is a DC simulation, capacitors are open-circuits.? No negative feedback around U1.? U3 seems to run into difficulty right in the vicinity of 0 V output, which is odd.
?
Even when the circuit is made smaller and it runs, it has considerable difficulty at certain operating points.? The SPICE output log is foll of warning messages that suggest it has trouble, and it suggests alternative settings to help.
?
Andy
?


Re: .MEAS Failure

 

?
Hello All:
?
Sorry for being late to the party but I had to grab some sleep time.
?
So, it's equality only.
No matter how many times I read the .meas help I would not come to that conclusion.
To me;?WHEN <expr> means WHEN <any and all types of mathematical experssion>.
WHEN <expr of equality only> would be much more redily understandable.
?
I noticed that there were no examples of anything like:
Print the time if and when a power exceeds 5W.
Print the time if and when a collector-emitter voltage goes less than 2V.
Print the time if and when a snubbed node ever exceeds 15.6V.
?
Those are always the type of questions that I regularly need answers to.
?
Thanks very much for the examples.
I will see if I can get the answers I need using only equality.
?
All for now

?
Sent:?Monday, February 24, 2025 at 11:24 AM
From:?"Tony Casey via groups.io" <tony@...>
To:[email protected]
Subject:?Re: [LTspice] .MEAS Failure
On 24/02/2025 15:57, Andy I via groups.io wrote:
But I distinctly recall Helmut Sennewald cautioning people not to test for equality.? Better to use >= or <=.? The implication was that it did not use linear interpolation in those situations.? I thought .MEAS was one of them.
This would be the case, for example, in a B-source expression, which disallows the "=" operator anyhow, e.g.:
?
B1 EQ0 0 V=if(V(test)=0,1,0)

..which triggers an error, but:
?
B1 EQ0 0 V=if(V(test)==0,1,0)

..doesn't.

However, in the example of my simple sine source circuit, the 2nd of those expressions only results in V(eq0)=1 once at time=0, because none of the following data points result in V(test)=0, even though it is clear the waveform is periodic and passes through zero twice every cycle. This example therefore doesn't use interpolation, it simply looks at each data point.

--
Regards,
Tony


Re: .MEAS Failure

 

开云体育

On 24/02/2025 15:57, Andy I via groups.io wrote:
But I distinctly recall Helmut Sennewald cautioning people not to test for equality.? Better to use >= or <=.? The implication was that it did not use linear interpolation in those situations.? I thought .MEAS was one of them.
This would be the case, for example, in a B-source expression, which disallows the "=" operator anyhow, e.g.:

B1 EQ0 0 V=if(V(test)=0,1,0)

..which triggers an error, but:

B1 EQ0 0 V=if(V(test)==0,1,0)

..doesn't.

However, in the example of my simple sine source circuit, the 2nd of those expressions only results in V(eq0)=1 once at time=0, because none of the following data points result in V(test)=0, even though it is clear the waveform is periodic and passes through zero twice every cycle. This example therefore doesn't use interpolation, it simply looks at each data point.

--
Regards,
Tony


Re: .MEAS Failure

 

mhx, sorry, I know better.
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I did not excluding anything via .save.
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.meas TRAN TooLow1 find V(XSW11:X1:Qc)-V(XSW11:X1:Qe) when V(XSW11:X1:Qc)-V(XSW11:X1:Qe)<1 still produces;
Measurement "toolow1" FAIL'ed
?
It's not the comma syntax. The above still fails even with full mathematical syntax.
?
I added a simple .meas statement using comma syntax and it works two levels deep.
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.meas Low1 MIN V(XSW11:X1:Qc,XSW11:X1:Qe)
low1: MIN(v(xsw11:x1:qc,xsw11:x1:qe))=0.00498581 FROM 0 TO 0.0500001
?
It is something to do with ".meas find when".
?
.meas TooLow1 find V(XSW11:X1:Qc)-V(XSW11:X1:Qe) when V(XSW11:X1:Qc)-V(XSW11:X1:Qe)<1
.meas TooLow2 find V(XSW11:X1:Qc,XSW11:X1:Qe) when V(XSW11:X1:Qc,XSW11:X1:Qe)<1
.meas TooLow3 find V(XSW11:X1:Qc)-V(XSW11:X1:Qe) when V(v+15)-V(v-15)>28
.meas TooLow4 find V(v+15)-V(v-15) when V(XSW11:X1:Qc)-V(XSW11:X1:Qe)<1
.meas TooLow5 find V(v+15,v-15) when V(XSW11:X1:Qc)-V(XSW11:X1:Qe)<1
.meas TooLow6 find V(XSW11:X1:Qc)-V(XSW11:X1:Qe) when V(v+15,v-15)>28
.meas TooLow7 find V(XSW11:X1:Qc) when V(v+15,v-15)>28
.meas TooLow8 find V(XSW11:X1:Qc) when V(XSW11:X1:Qe)<1
?
Measurement "toolow1" FAIL'ed
Measurement "toolow2" FAIL'ed
Measurement "toolow3" FAIL'ed
Measurement "toolow4" FAIL'ed
Measurement "toolow5" FAIL'ed
Measurement "toolow6" FAIL'ed
Measurement "toolow7" FAIL'ed
Measurement "toolow8" FAIL'ed

All for now

?
?
Sent:?Monday, February 24, 2025 at 5:24 AM
From:?"mhx via groups.io" <mhx@...>
To:[email protected]
Subject:?Re: [LTspice] .MEAS Failure
No, that is not what I said ...
.MEAS TRAN TooLow1 find V(XSW11:X1:Qc ) - V( XSW11:X1:Qe) when V(XSW11:X1:Qc ) - V( XSW11:X1:Qe) < 1
(may need extra parentheses).

A final one: Do you have a .SAVE statement somewhere?

-marcel




?


Re: intuition behind a solution to crashing time domain simulation #Time-step-too-small

 

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I agree, of course, but the AD797 is a (costly) opamp. It should not produce a TSTS error in that .ASC. Without a lot of digging, it isn't possible to confirm that it is connected correctly; for example, is node 38 really the output? The .ASC appears to work with the simple opamp.. It could hardly refuse.

On 2025-02-24 14:52, Andy I via groups.io wrote:
On Mon, Feb 24, 2025 at 09:03 AM, john23 wrote:
Hello ,I have the following file which is presenting an error shown below
...
Convergence Failure: ?Time step too small; time = 8.11724e-08, timestep = 1.25e-19: trouble with instance "u1:DSC1"
I assume this is the failure you asked about.
?
"Time step too small" errors are unfortunately difficult to deal with.? If this is your first time encountering a "timestep too small" error, "welcome to the club".
?
"Time step too small" errors happen for this reason.? When SPICE can't converge at any timepoint, it backs up to the previous one, sets the time step smaller (I think by a factor of 8), and tries again.? It is more likely to find convergence by not trying to go too far into the future, so a smaller timestep after the last good point is more likely to solve, and then it can move on.
?
But occasionally that doesn't work.? It keeps trying smaller and smaller timesteps, until eventually the timestep gets ridiculously small, and SPICE/LTspice aborts with that error message.
?
The root problem is most likely because there is something in the circuit that behaves badly.? Maybe a component's function or its derivative has a discontinuity.? Both are bad for SPICE and should never happen, but many models have discontinuities and can lead to these problems.? The best remedy is to fix the models.? But often we can't do that.? There are a handful of other things that can sometimes help,?
?
Download the FAQ file.? Open it and read until you find the section about "time step too small" errors, and start reading.? There are a couple dozen suggestions that MIGHT help.? There is no guarantee that you can ever fix a "time step too small" error.
?
When I ran your simulation, I do not (yet) have a "time step too small" error, but it has not found the initial DC solution yet.? Time step too small errors can happen even during the initial DC solution phase, because one of the algorithms is "Pseudo-Tran", which applies the transient solver to finding the DC solution.? Sometimes it can abort in that phase, even though it is not a .TRAN simulation at all.
?
Andy
?
?
--
OOO - Own Opinions only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion

Virus-free.


Re: Initial conditions for inductor current in .TRAN UIC analysis - follow up

 

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I think it does look like a paradox. It one were doing a Laplace analysis with pencil and paper, I(L1)? = 10 A would definitely be an 'initial condition'. But I did conclude that it isn't in LTspice.

On 2025-02-24 14:30, Andy I via groups.io wrote:
On Mon, Feb 24, 2025 at 09:11 AM, John Woodgate wrote:

On the face of it, setting IC of L1 = 10, but also specifying UIC is paradoxical.

That is actually normal for SPICE syntax.? Specifying UIC tells SPICE to definitely use that IC setting.? No paradox.
?
There may be some difference in the details, between how different SPICE programs handle it.? But I think it is basically like this:? Specifying initial conditions (either IC= or .IC) works differently depending on whether UIC is also used.? Without UIC, SPICE applies the initial conditions, lets the circuit converge, then it might remove the enforcing conditions and lets it converge again.? Therefore, whether or not it does the second step, it starts with a self-consistent set of voltages and currents.? Whereas, when you add UIC, SPICE omits trying to converge.? It just accepts the initial conditions you specify (including 0 for any not specified), and accepts them as is.? ?No attempt to solve the network equations with those conditions.? Therefore it is almost guaranteed to "burp" when the transient simulation begins.? You got what you asked for, even if it is garbage.
?
I can't guarantee that what I described above happens in all SPICE programs, but this was my understanding, from decades ago.
?

I suppose IC = 10 doesn't count as an 'initial condition' despite the name.

It does count as an "initial condition".? But it needs to be taken with care.
?
Andy
?
--
OOO - Own Opinions only If something is true: * as far as we know - it's science *for certain - it's mathematics *unquestionably - it's religion


Re: .MEAS Failure

 

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On 24/02/2025 16:25, Tony Casey wrote:
.MEAS T1 when V(test)=0
.MEAS T2 when V(test)<>0
.MEAS T3 when V(test)>=0
.MEAS T4 when V(test)<=0
.MEAS T5 when V(test)<0
.MEAS T6 when V(test)<0
Sorry, copy-paste error. Should have been:
.MEAS T1 when V(test)=0
.MEAS T2 when V(test)<>0
.MEAS T3 when V(test)>=0
.MEAS T4 when V(test)<=0
.MEAS T5 when V(test)<0
.MEAS T6 when V(test)>0
Same result.

--
Regards,
Tony



Re: Initial conditions for inductor current in .TRAN UIC analysis - follow up

 

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Yes, that was my conclusion.

On 2025-02-24 14:29, Carlo wrote:
On Mon, Feb 24, 2025 at 06:11 AM, John Woodgate wrote:
On the face of it, setting IC of L1 = 10, but also specifying UIC is paradoxical. I suppose IC = 10 doesn't count as an 'initial condition' despite the name. Evidence of this is the huge voltage spike at t = 0, which presumably is the way that the 10 A current is produced instantaneously.
No, IC=10 at inductor component level does count as inductor's current initial condition for .TRAN UIC analysis. Indeed the v1 voltage spike at 2nd datapoint (not at the first) changes according that IC= initial condition. Check the result for instance changing IC=10 to IC=1.
?
It basically affects the value of the derivative di/dt at the 2nd datapoint.
?
Carlo.
--
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Re: .MEAS Failure

 

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On 24/02/2025 15:57, Andy I via groups.io wrote:
On Mon, Feb 24, 2025 at 09:48 AM, Tony Casey wrote:
... The LTspice just takes the two closest data points and performs linear interpolation to establish when the expression is true. ...
That might be true.? But I distinctly recall Helmut Sennewald cautioning people not to test for equality.? Better to use >= or <=.? The implication was that it did not use linear interpolation in those situations.? I thought .MEAS was one of them.
?
Perhaps I remembered incorrectly.
I think you're missing the point I made in the first response. This type of .MEAS is designed to find a single point on the x-axis when an expression is true. None of the .MEAS examples in the Help use any operator other than "=". Everything else is an inequality, which returns an interval.

E.g.:

.MEAS TRAN res6 WHEN V(x)=3*V(y)

Print the first time the condition V(x)=3*V(y) is met. This will be labeled res6.

.MEAS can perform a calculation over an interval, but still returns a single result.

Simple example of a sine wave source:

.MEAS T1 when V(test)=0
.MEAS T2 when V(test)<>0
.MEAS T3 when V(test)>=0
.MEAS T4 when V(test)<=0
.MEAS T5 when V(test)<0
.MEAS T6 when V(test)<0
Only T1 can return a single result:
LTspice 24.0.12 for Windows
Circuit: * U:\Simulations\LTspice\Lib\sub\Draft1.asc
Start Time: Mon Feb 24 16:20:42 2025
solver = Normal
Maximum thread count: 32
tnom = 27
temp = 27
method = modified trap
.OP point found by inspection.

t1: v(test)=0 AT 0

Measurement "t2" FAIL'ed

Measurement "t3" FAIL'ed

Measurement "t4" FAIL'ed

Measurement "t5" FAIL'ed

Measurement "t6" FAIL'ed

Total elapsed time: 0.051 seconds.

--
Regards,
Tony


Re: Initial conditions for inductor current in .TRAN UIC analysis - follow up

 

On Mon, Feb 24, 2025 at 09:49 AM, Carlo wrote:
What do you mean by
... then it might remove the enforcing conditions and lets it converge again
I mean that it might remove the IC= or .IC enforced conditions, and run another pass looking for convergence.
?
Whether or not it does that, is not the point I was making.? The point is that it begins the transient analysis by starting at a consistent operating point where convergence was reached.
?
Andy
?