On Mon, Feb 24, 2025 at 11:11 AM, John Woodgate wrote:
I agree, of course, but the AD797 is a (costly) opamp. It should not produce a TSTS error in that .ASC.
Why not?
Does expensive silicon imply an equally expensive SPICE model?? Shouldn't every SPICE model ever made, whether for cheap or expensive silicon, not produce time step too small errors?? And yet they happen.
Without a lot of digging, it isn't possible to confirm that it is connected correctly; for example, is node 38 really the output?
The SPICE model claims that it is.? What is your point with that question?? Are you suggesting that its creator at AAG/PMI did not know what she/he was doing, and mis-labeled the output node?? If that happened, then there would be an awful lot more questions than that one.
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I think simpler circuits are in order for this simulation.? Realizing that U1 is open-loop might be a good first step.? Since this is a DC simulation, capacitors are open-circuits.? No negative feedback around U1.? U3 seems to run into difficulty right in the vicinity of 0 V output, which is odd.
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Even when the circuit is made smaller and it runs, it has considerable difficulty at certain operating points.? The SPICE output log is foll of warning messages that suggest it has trouble, and it suggests alternative settings to help.
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