Re: schematic erorr download from internet
goy123t wrote, "anybody can explain to me?what's it?"
It's an LTspice schematic!? That is what the schematic's file actually looks like.
You just opened it in the wrong program (a text editor instead of LTspice).? As John says, that probably happened because it got downloaded with a ".txt" filename extension added to it.? So, rename it to get rid of the .txt.? If you can't see the .txt, then you must have your Windows set up to "Hide extensions for known file types", which is a really BAD (in my opinion) Windows setting.
Regards, Andy
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goy123t, your waveform was not very sinusoidal, so it was no surprise that the FFT came out badly.? Always use a whole integer number of cycles.
Imagine doing this:? Take your simulated waveform, and glue the end of the waveform and ithe beginning of the waveform to each other.? That's the thing that the FFT effectively operates on.? If you splice your original waveform like that, you wouldn't get a sine wave.
Please see the FFT example in LTspice's Help: ? ? Help: Waveform Viewer > Waveform Arithmetic
Notice the use of ".options plotwinsize=0" which you should ALWAYS have when preparing to do an FFT.
Using .options numdgt=15 is "icing on the cake" and not normally needed.
Total time (= Stop time - Time to start saving data) should always be a whole number of cycles of your signal.? I recommend starting with about 10 whole cycles.? 1 is bare minimum but not very satisfactory in the FFT display.? 100 cycles is OK but you be the judge on that.? If two or more signals are present, find a time interval that works for both frequencies, which is also related to the difference in frequencies.
Time_step is best being "as small as possible."? Ideally, waveforms would be continuous, so the closer together the time points are, the better.? But very small time_step makes the simulation run slowly.? There's your main trade-off.? And always combine it with ".options plotwinsize=0" so that you aren't throwing away most of those time steps.
Number of samples?? Which one do you mean?
If it's "Number of data point samples in time", experiment with that.? More samples gives you an FFT that goes up higher in frequency, but it might be meaningless data at that end of the spectrum.? When the time interval between those "data point samples in time" becomes smaller than the simulated time_step, then the FFT is just interpolating between the available data, which is not real.
If it's "Number of points" of Binomial Smoothing, I usually change that to 1.? This setting does a bit of smoothing before calculating the FFT.? If your waveforms are noisy, then bigger numbers may help; but it causes the high frequency end of the FFT to fall off more.
? ? "third question : if fft used the values from transient analysis, the time step in tran. analysis effect result of fft and how?"
I think this was already answered.? The smaller the time_step, the more continuous the data is, that gets sent to the FFT.? There is no waveform data between time_steps, so the FFT has to guess what the waveform would have been, between those time_steps.? Smaller time_steps means the guesses are probably more accurate because they are closer to the actual simulated points in time.
So, the time_step will mainly affect the harmonics at higher frequencyes; but not the fundamental.
Regards,
Andy
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Re: timestep size effect (surprising?)
Hello John,
I think the simulation is precise. The measured average value is 20.182uV whereas the ideal value would be 20uV. The pulsewidth is effectively 2fs due to its 1fs rise time, 1fs wdth and 1fs fall time.
When I force the timestep to 1n, the average will be 20.032us which is very close to 20uV.
.tran 0 50u 0 1n .options plotwinsize=0
Best regards, Helmut
---In LTspice@..., <jmw@...> wrote : I still see very odd behaviour of the voltage
across C? with 400 cycles and 50 ?s simulation time. But the
attenuation of these very short pulses is huge (1 kV down to 20
?V), so are there 'rounding errors'? The 12 ?V DC offset is
notable.
Best wishes
John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates
Rayleigh, Essex UK
?Hello Eamon,
I just uploaded the file "_pulse charge
accumulation.asc" with this option.
Best regards, Helmut
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Re: timestep size effect (surprising?)
I still see very odd behaviour of the voltage
across C? with 400 cycles and 50 ?s simulation time. But the
attenuation of these very short pulses is huge (1 kV down to 20
?V), so are there 'rounding errors'? The 12 ?V DC offset is
notable.
Best wishes
John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates
Rayleigh, Essex UK
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Hello Eamon,
I just uploaded the file "_pulse charge
accumulation.asc" with this option.
Best regards,
Helmut
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Re: encapsulating a long set of spice directives
Steph, you probably know this already, but I'll mention it anyway, just in case.
The long list of .PARAM statements can also be shortened by combining multiple parameter assignments into the same line.
Of course you lose the ability to document each one with a comment.? And it makes them generally less readable.
Regards, Andy
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Re: Is it possible to dynamically change a part's location in one simulation ?
LTspice has a limited ability to .STEP through different models for the same part.? But it's somewhat risky.
You can use .STEP to change a transistor's (or diode's) .MODEL, if you define those .MODELs with numeric names: ? ? .MODEL 1 NPN (...)
? ? .MODEL 2 NPN (...) and so on.
The same thing SOMETIMES works for subcircuits too, if you're careful, using numeric subcircuit names.? However, if the subcircuits differ in a substantial way, then it fails, without warning.? I believe the problem is that LTspice reserves memory for the network's matrix once, and uses the same memory space for all .STEPped runs.? So if the subcircuits use a different amount of memory, or structure it differently, LTspice may end up walking all over its own memory and it corrupts the data.
I think it is much safer to either run consecutive simulations (each with their own schematic or netlist), or combine circuits into the same schematic.? You make it sound like combining circuits is very inefficient.? Often it is not.? Don't dismiss it if it may work.
Regards, Andy
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Re: timestep size effect (surprising?)
Hello Eamon,
I just uploaded the file "_pulse charge accumulation.asc" with this option.
Best regards, Helmut
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Re: timestep size effect (surprising?)
Hello Eamon,
LTspice use data compression by default to reduce the size of the output file (.raw). This makes sense for the simulation of DC/DC converters.
One should turn off data compression for analog simulations. See the SPICE-directive below. Now the simulation looks OK.
.options plotwinsize=0
Best regards, Helmut
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Hi Bordodynov, Thank you for your instructions. I think I'm still not up to speed right now on these kinds of operation. I was able to locate the ZZZ files and just added it to the sym directory of my LTspice XVII. So I could see all the symbols that is in there. I also added the .lib files to my LTspice XVII sub directory.? I'm not sure how the symbols on the sym directory will be able to locate their matching?? .lib models in the sub directory. So far what I have done for symbol mc34072 is to add MC34071.lib to the model file attributes and it works. I still have to chew a lot to be able to digest what is? in front of me. I'll just take on the parts that are of interest to me one piece at time and see how it goes. And I wouldn't want to bother you any further but may ask for future help.again. Thanks and best regards, Eric
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Hi Eric. I organized my library in an alternative way, not as recommended in this group. I have all the characters inside me have a link to the library file. Almost all library files are in the folder \ \ Documents \ LTspiceXVII \ lib \ sub, and the symbols are in the \ Documents \ LTspiceXVII \ lib \ sym \ ZZZ folder. All this is on my page. My option allows you to immediately draw a diagram, do not bother about links to the library. By the way, I have different characters in folders for logic without power and with a power source. If you want to follow the traditions of this group, then I re-recommend using the following algorithm: 1. Create a new project folder. 2. Copy the non-standard symbols from the ZZZ / ... folder to this folder. 3. open characters one by one and read the last line. There is a library file name. 4. Copy this library to the project folder from the SUB folder. And so for each character. This is due to the fact that the name of the library and the name of the symbol are different and in one library can be designed for several different characters. 5. Draw the scheme and model. There are exceptions to paragraph 4. For example, the bottom line is empty, and in the SpiceModel line you will see something like this: .. \ sym \ ZZZ \ MOS \ IRF \ LIB \ irlz44zsl.spi. This is the model file with indirect addressing. If you want to send a project to a group, then zip the project folder in a ZIP format and upload it to the TEMP folder. I have to do this if I want to share my project. This is the inconvenience of my way of organizing libraries. But in my case, I try to put together a "gang" of like-minded people and the exchange of data is very simplified. All that is needed is everyone has my library. Then do not do the above procedure. In the Russian segment of the Internet act in a similar way. By the way, I took some models from there, reorganized them and added many other models. ? Bordodynov.
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Hi Bordodynov, Thank you for your help. I went to your ltwiki link. It's mind boggling the volume of work you have done. Thanks for sharing to us. Some of the parts were in my wish list. I'm still trying to figure though how to download the ZZZ symbols file?
Thanks and best regards, Eric
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Hi Eric. I opened your circuit and everything was modeled. I just did: .tran 0 10m 0 uic I have installed libraries in ../Documenty/LTspiceXVII/ .. You can find it on my page: ? Bordodynov
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Hi Helmut, Do you happen to have still the "74hc_v.lib file" used in the "74194 test.asc" schematic? It is not inside the zip file so I could not load it into the "sub" directory. The schematic would not run and is looking for it.. I tried working through your instruction how to convert a .asc file into ..lib but was too heavy for me. I reloaded the file dated Nov 19, 2016 for reference. I wrote an ealier email but seems did not go thru. Thanks and best regards, Eric ? ? ? ? ? ? ? ? ? ? ? ?
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Re: schematic erorr download from internet
Hello,
I have the same problems sometimes. It has only happened when I directly tried to open a schematic from the Internet. It always has helped to download the file to the harddisk. Then I have been able to open it with LTspice.
Best regards, Helmut
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Re: schematic erorr download from internet
That's because it has had a .TXT extension
added in error, possibly by your browser, like: foobar.asc.txt.?
Don't try to open it directly from the web site. Save it and
then open it in LTspice. Of course, if the real filename is
foobar.net.txt, it really is a netlist, not a schematic.
Best wishes
John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates
Rayleigh, Essex UK
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hi
sometimes when in site i search i see some link to
schematic in ltspice, but when i download? it seems
like:
ersion 4
SHEET 1 1224 680
WIRE 176 -64 0 -64
WIRE 304 -64 176 -64
WIRE 512 -64 384 -64
WIRE 0 -16 0 -64
WIRE 176 -16 176 -64
WIRE 0 112 0 48
WIRE 0 112 -176 112
WIRE -176 160 -176 112
WIRE -176 304 -176 240
WIRE 176 304 176 48
WIRE 176 304 -176 304
WIRE 0 368 0 112
WIRE 176 368 176 304
WIRE 0 496 0 432
WIRE 176 496 176 432
WIRE 176 496 0 496
WIRE 256 496 176 496
WIRE 512 496 512 -64
WIRE 512 496 256 496
WIRE 256 528 256 496
FLAG 256 528 0
SYMBOL current 304 -64 R270
WINDOW 0 32 40 VTop 2
WINDOW 3 -32 40 VBottom 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value PWL file=Quasi.txt
SYMBOL voltage -176 144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.05
SYMATTR InstName V1
SYMATTR Value SINE(0 325.2 50)
SYMBOL diode 16 48 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value MUR460
SYMBOL diode 192 48 R180
?anybody can explain to me?what's it?
thanks a lot.
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timestep size effect (surprising?)
Could someone please have a look at the extremely simple simulation I?uploaded as "pulse charge accumulation.asc" and tell me what you think.
It's a transient analysis of a positive pulse voltage source followed by an RC filter. The notable oddity is that in the aftermath of the 10 (very short) pulses, the capacitor voltage shows a few more inflection points than I would expect, and actually goes negative for a little bit of time.?
The issue goes away when I make the pulses wider, or when I set the max timestep to 100pS, but I really wonder why the simulator has problems with an RC discharge. (If the problem is that the timestep is too large, why would this be brought on by simulating extremely FAST pulses?)
Best regards,
Eamon
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schematic erorr download from internet
hi sometimes when in site i search i see some link to schematic in ltspice, but when i download? it seems like:
ersion 4 SHEET 1 1224 680 WIRE 176 -64 0 -64 WIRE 304 -64 176 -64 WIRE 512 -64 384 -64 WIRE 0 -16 0 -64 WIRE 176 -16 176 -64 WIRE 0 112 0 48 WIRE 0 112 -176 112 WIRE -176 160 -176 112 WIRE -176 304 -176 240 WIRE 176 304 176 48 WIRE 176 304 -176 304 WIRE 0 368 0 112 WIRE 176 368 176 304 WIRE 0 496 0 432 WIRE 176 496 176 432 WIRE 176 496 0 496 WIRE 256 496 176 496 WIRE 512 496 512 -64 WIRE 512 496 256 496 WIRE 256 528 256 496 FLAG 256 528 0 SYMBOL current 304 -64 R270 WINDOW 0 32 40 VTop 2 WINDOW 3 -32 40 VBottom 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName I1 SYMATTR Value PWL file=Quasi.txt SYMBOL voltage -176 144 R0 WINDOW 123 0 0 Left 2 WINDOW 39 24 124 Left 2 SYMATTR SpiceLine Rser=0.05 SYMATTR InstName V1 SYMATTR Value SINE(0 325.2 50) SYMBOL diode 16 48 R180 WINDOW 0 24 64 Left 2 WINDOW 3 24 0 Left 2 SYMATTR InstName D2 SYMATTR Value MUR460
SYMBOL diode 192 48 R180
?anybody can explain to me?what's it? thanks a lot.
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Modeling gate capacitance of a FET
Hello,
Using the NMOS level 3 FET. How do I define the parasitic capacitances like Cgs?? I've found elsewhere, not in the help file, that Cgs=Cgso x W or (overlap) times (channel width). If you know Cgs from the real datasheet and say W=1u then you can calculate Cgso and define it in the .model directive.
Is Cgs then implied by LTSPICE after defining Cgso? Or do I need to wrap it externally by a cap within a .subckt directive?? Is this the most direct/convenient way or have I missed something?
Thanks, Gilbert
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Re: Model for F0800LC180 PUK diode
Hello jlopez,
this might serve as a starting point in modeling the diode:
.model F0800LC180 D(Is=500 Rs=390u N=5.34 Ikf=480u Isr=4.2e-30?Cjo=100p
Tt=90n BV=1800 Iave=775 Vpk=1800 mfg=Westcode type=silicon)
It models the U/I-characteristic, reverse current, breakdown and reverse recovery. However, it is not tested and the value of Cjo might need some adjustment, as the data sheet gives no indication of the reverse capacitance
of the diode. You might need to set up some simulation test cicuits with this model to refine it further to reach accordance with the datasheet data.
Best regards
Gerhard Kaufmann
Von: LTspice@... im Auftrag von jlopez2022@... [LTspice]
Gesendet: Dienstag, 27. November 2018 16:30
An: LTspice@...
Betreff: [LTspice] Model for F0800LC180 PUK diode
?
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I am looking for a model for that diode or the way to obtain it. I like that diode because its price is not so high and reach 775A averaged and 1800V.
The specs can be found here, appear the Trr that is important in the design of a high power rectifier:
?
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www.westcode.com
WESTCODE An IXYS Company Extra Fast Recovery Diode Type F0800LC180 Provisional Data Sheet. Type F0800LC180 Issue 1 Page 4 of 11 February, 2004 5.0 Reverse Recovery Loss The following procedure is recommended for use where it is necessary to include reverse
recovery loss.
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If you do an FFT of just half a sine wave,
that's what you get. If you change 5 ?s to 50?s and do the FFT
you will see the strong line at 100 kHz and a lot of 'noise' at
much lower levels.
You should always simulate, if possible, for a
whole number of cycles of every signal you are analysing. That
may require many cycles, e.g. if you have 100 kHz and 105 kHz.
Time step should be 1 % of the period? of the highest frequency, or
less.
The time-step affects the number of points in
a cycle that are evaluated. To minimize computation noise,
evaluate many points.
Best wishes
John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates
Rayleigh, Essex UK
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hi
i wanted to use fft in ltspice for a sin wave(schamtic
attached with name as : fft_sine_wave) . i saw that i have
other frequency in fft result, why?
second question: for a input signal with specific
frequency, how value we select? total time and? time_step
and number of sample?
third question : if fft used the values from transient
analysis, the time step in tran. analysis effect result of
fft and how?
thanks
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Re: Is it possible to dynamically change a part's location in one simulation ?
Hi, John:
But it becomes very slow, and seems never get the goal/final step, if put many similar circuits in same schematic, too many redundant portions/actions, make it very inefficiency.
Ironically, I need to see how those wonky architecture of TTLs badly ruin the system, and analyze which part/location is the worst, and understand more detail of the characteristic of BJTs, why they can't behave same as CMOSs in digital/modern computing domain. And maybe, unfortunately learn 'how to let go', though I don't know why should I do that, maybe just some subjects in the future I will need, I tend to think more when I am in free time.
But I think you have gave the answer, it's impossible. Thus, I backup another file, everytime when I try to run those kind of simulations, I resume it will fail at the final, so that maybe after decades times I will give up, then I will use the backup to recovery the ruin one which already shown how badly it was.
That's the whole story, but I still think the wonky one will be still wonky. Never evolution automatically. ---In LTspice@..., <jmw@...> wrote : You can do it indirectly by putting several
circuits in one .ASC file, with the components in different
positions, and running the .ASC.
Best wishes
John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates
Rayleigh, Essex UK
?Hi, :
It occurred to me, and confused me a while,
typically I hope to dynamically change a part's location
in the schematic of LTspice when I am running
simulation, that means different circuit topologies but
similar, it helps to "batch" those result in one-click
simulation. Like the 'step' directives, but step doesn't
support different topology (part's location).
I never used that, but I think if it's possible,
that would be great. Actually, more great stuff is the parts (which
change locations) could be changed their 'model', I mean
dynamically change, eg: R -> C, C->L, etc, and the
polarities. Like the '.list' directives, but '.list'
only change the fixed part's intrinsic value.
Though it's almost impossible, but I better ask one
time to get the exact answer. Which maybe I could
inherit something, maybe store it in my mind.
Thank you very much. Have a nice day!
Best regards.
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hi i wanted to use fft in ltspice for a sin wave(schamtic attached with name as : fft_sine_wave) . i saw that i have other frequency in fft result, why? second question: for a input signal with specific frequency, how value we select? total time and? time_step and number of sample? third question : if fft used the values from transient analysis, the time step in tran. analysis effect result of fft and how?
thanks
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No offence was taken.
Your filter package is an outstanding piece of work.
I should take note of this and put my contributions to you *before* I
publish. :-) I think I'll need a week's worth of time for my foot to recover from the pulling... :-) -- Vlad ______________________ ltspicegoodies.ltwiki.org -- holding, among others: a universal analog/digital filter, block-level models for power electronics (and not only), math blocks with a more stream-lined approach, some digital ADC, DAC, (synchronous-)counter, JKflop, etc.
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John Woodgate